データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

ISL1218IUZ データシート(PDF) 9 Page - Intersil Corporation

部品番号 ISL1218IUZ
部品情報  Low Power RTC with Battery Backed SRAM
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL1218IUZ データシート(HTML) 9 Page - Intersil Corporation

Back Button ISL1218IUZ Datasheet HTML 5Page - Intersil Corporation ISL1218IUZ Datasheet HTML 6Page - Intersil Corporation ISL1218IUZ Datasheet HTML 7Page - Intersil Corporation ISL1218IUZ Datasheet HTML 8Page - Intersil Corporation ISL1218IUZ Datasheet HTML 9Page - Intersil Corporation ISL1218IUZ Datasheet HTML 10Page - Intersil Corporation ISL1218IUZ Datasheet HTML 11Page - Intersil Corporation ISL1218IUZ Datasheet HTML 12Page - Intersil Corporation ISL1218IUZ Datasheet HTML 13Page - Intersil Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 21 page
background image
9
FN6313.0
June 22, 2006
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer. The ISL1218 provides on-chip
crystal compensation networks to adjust load capacitance to
tune oscillator frequency from -94ppm to +140ppm. For
more detailed information see the Application Section.
Single Event and Interrupt
The alarm mode is enabled via the ALME bit. Choosing
single event or interrupt alarm mode is selected via the IM
bit. Note that when the frequency output function is enabled,
the alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ pin will be pulled low and the
alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ pin will be pulled low for 250ms and the alarm
status bit (ALM) will be set to “1”.
NOTE: The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit).
The alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see the Alarm Registers Description.
Frequency Output Mode
The ISL1218 has the option to provide a frequency output
signal using the IRQ/FOUT pin. The frequency output mode
is set by using the FO bits to select 15 possible output
frequency values from 0 to 32kHz. The frequency output can
be enabled/disabled during battery backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL1218 provides 8 bytes of user SRAM. The SRAM will
continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
I2C Serial Interface
The ISL1218 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bidirectional data
signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL1218 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated
compensation of approximately -34ppm to +80ppm. (See
ATR description.)
2. A digital trimming register (DTR) that can be used to
adjust the timing counter by ±60ppm. (See DTR
description.)
Also provided is the ability to adjust the crystal capacitance
when the ISL1218 switches from VDD to battery backup
mode. (See Battery Mode ATR Selection for more details.)
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:19h]. The defined addresses and default values are
described in the Table 1. Address 09h is not used. Reads or
writes to 09h will not affect operation of the device but should
be avoided.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 4 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
4. User SRAM (8 bytes): Address 12h to 19h.
There are no addresses above 19h.
ISL1218


同様の部品番号 - ISL1218IUZ

メーカー部品番号データシート部品情報
logo
Renesas Technology Corp
ISL1218IUZ RENESAS-ISL1218IUZ Datasheet
883Kb / 21P
   Low Power RTC with Battery Backed SRAM
ISL1218IUZ-T RENESAS-ISL1218IUZ-T Datasheet
883Kb / 21P
   Low Power RTC with Battery Backed SRAM
More results

同様の説明 - ISL1218IUZ

メーカー部品番号データシート部品情報
logo
Intersil Corporation
ISL1208 INTERSIL-ISL1208_06 Datasheet
348Kb / 21P
   Low Power RTC with Battery Backed SRAM
ISL1208IRT8Z INTERSIL-ISL1208IRT8Z Datasheet
406Kb / 24P
   Low Power RTC with Battery Backed SRAM
logo
Renesas Technology Corp
ISL1218 RENESAS-ISL1218 Datasheet
883Kb / 21P
   Low Power RTC with Battery Backed SRAM
logo
Intersil Corporation
ISL12022MR5421 INTERSIL-ISL12022MR5421 Datasheet
401Kb / 29P
   Low Power RTC with Battery Backed SRAM, Integrated 5ppm
ISL1221 INTERSIL-ISL1221 Datasheet
649Kb / 24P
   Low Power RTC with Battery Backed
ISL1209 INTERSIL-ISL1209 Datasheet
416Kb / 24P
   Low Power RTC with Battery Backed SRAM and Event Detection
ISL1219 INTERSIL-ISL1219 Datasheet
643Kb / 24P
   Low Power RTC with Battery Backed SRAM and Event Detection
ISL1209 INTERSIL-ISL1209_06 Datasheet
358Kb / 24P
   Low Power RTC with Battery Backed SRAM and Event Detection
logo
Renesas Technology Corp
ISL1219 RENESAS-ISL1219 Datasheet
994Kb / 24P
   Low Power RTC with Battery Backed SRAM and Event Detection
ISL1209 RENESAS-ISL1209 Datasheet
998Kb / 25P
   Low Power RTC with Battery Backed SRAM and Event Detection
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com