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AD1939YSTZRL データシート(PDF) 9 Page - Analog Devices |
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AD1939YSTZRL データシート(HTML) 9 Page - Analog Devices |
9 / 32 page AD1939 Rev. 0 | Page 9 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND 1 MCLKI/XI 2 MCLKO/XO 3 AGND 4 AVDD 5 OL3P 6 OL3N 7 OR3P 8 OR3N 9 OL4P 10 OL4N 11 OR4P 12 OR4N 13 PD/RST 14 DSDATA4 15 DGND 16 AGND 48 FILTR 47 AGND 46 AVDD 45 AGND 44 OR2N 43 OR2P 42 OL2N 41 OL2P 40 OR1N 39 OR1P 38 OL1P 36 CLATCH/ADR1 35 CCLK/SCL 34 DGND 33 OL1N 37 AD1939 TOP VIEW (Not to Scale) DIFFERENTIAL OUTPUT NC = NO CONNECT Figure 2. 64-Lead LQFP, Differential Output, Pin Configuration Table 10. Pin Function Descriptions Pin No. In/Out Mnemonic Description 1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 4 I AGND Analog Ground. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 O OL3P DAC 3 Left Positive Output. 7 O OL3N DAC 3 Left Negative Output. 8 O OR3P DAC 3 Right Positive Output. 9 O OR3N DAC 3 Right Negative Output. 10 O OL4P DAC 4 Left Positive Output. 11 O OL4N DAC 4 Left Negative Output. 12 O OR4P DAC 4 Right Positive Output. 13 O OR4N DAC 4 Right Negative Output 14 I PD/RST Power-Down Reset (Active Low). 15 I/O DSDATA4 DAC Input 4 (Input to DAC 4 L and R)/DAC TDM Data Out 2/AUX ADC 1 Data In. 16 I DGND Digital Ground. 17 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 18 I/O DSDATA3 DAC Input 3 (Input to DAC 3 L and R)/DAC TDM Data In 2/Aux DAC 2 Data Output. 19 I/O DSDATA2 DAC Input 2 (Input to DAC 2 L and R)/DAC TDM Data Out 1/AUX ADC 1 Data In. 20 I DSDATA1 DAC Input 1 (Input to DAC 1 L and R)/DAC TDM Data In 1/AUX ADC 2 Data In. 21 I/O DBCLK Bit Clock for DACs. 22 I/O DLRCLK LR Clock for DACs. 23 I VSUPPLY +5 V Input to Regulator, Emitter of Pass Transistor. 24 I VSENSE +3.3 V Output of Regulator, Collector of Pass Transistor. |
同様の部品番号 - AD1939YSTZRL |
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同様の説明 - AD1939YSTZRL |
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