FM20L08 - Extended Temp.
Rev. 1.4
Oct. 2005
Page 8 of 14
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
Power Supply Voltage with respect to VSS
-1.0V to +5.0V
VIN
Voltage on any signal pin with respect to VSS
-1.0V to +5.0V and
VIN < VDD+1V
TSTG
Storage Temperature
-55
°C to +125°C
TLEAD
Lead Temperature (Soldering, 10 seconds)
300
° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only, and the functional operation of the device at these or any other conditions above those listed in the
operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
DC Operating Conditions (TA = -25° C to +85° C, VDD = 3.3V +10%, -5% unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Power Supply
3.135
3.3
3.63
V
IDD
VDD Supply Current
-
22
mA
1
ISB
Standby Current – CMOS
-
20
µA
2
VTP
VDD trip point to assert (deassert) /LVL
2.7
-
3.0
V
3
ILI
Input Leakage Current
±1
µA
4
ILO
Output Leakage Current
±1
µA
4
VIH
Input High Voltage
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.6
V
VOH
Output High Voltage (IOH = -1.0 mA)
2.4
-
V
VOL
Output Low Voltage (IOL = 2.1 mA)
-
0.4
V
5
Notes
1.
VDD = 3.6V, /CE cycling at minimum cycle time. All inputs at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded.
2.
VDD = 3.6V, /CE at VDD, All other pins at CMOS levels (0.2V or VDD-0.2V).
3.
This is the VDD trip voltage at which /LVL is asserted or deasserted. When VDD rises above VTP, /LVL will be deasserted
after satisfying tPULV. When VDD drops below VTP, /LVL will be asserted after satisfying tPDLV.
4.
VIN, VOUT between VDD and VSS.
5.
For the /LVL pin, the test condition is IOL = 80 µA when VDD is between 3.135V and 1.2V. The state of the /LVL pin is not
guaranteed when VDD is below 1.2V.