10
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
The factory default setting for the configuration register is
CF8-CF0 is: 0 0000 1001 B (write protect range = none, read
uses falling edge of the clock, and pin 1 = no connect). Bits
CF15-CF9 are reserved. When writing to the configuration
register CF15-CF9 should be 0. When reading, the settings
of CF15-CF9 should be ignored.
Write Protect Range and Direction, WR[3:0], WD
The write protect range and direction bits WR[3:0] and WD
are located at configuration bits CF[7:4] and CF[3] respec-
tively. The write protect range and direction bits select how
the array is protected. They work in conjunction with the
WP input pin, valid only if WP is inactive (high). WR[3:0]
can select write protection of all sectors, none of the
sectors, or specific sectors grouped in blocks of 32
(~8 KB). The WD bit specifies whether the protected block
range starts from the first sector, address 0 (000H), or from
the last sector (1FFH for the NX25F011B, 3FFH for the
NX25F021B, and 7FF for the NX25F041B). Table 2A, 2B
and 2C lists the write protect sector range for the devices.
Once protected, all further writes to sectors within the
range will be ignored. The factory default setting is with no
write protected sectors, WR=[0,0,0,0] and WD=1.
Read Clock Edge, RCE
The Read Clock Edge bit (RCE) is located at configuration
bit location CF[2]. It selects which edge of the clock (SCK)
is used while reading data out of the device. Although the
SPI protocol specifies that data is written during the rising
edge and read on the falling edge of the clock, if required,
the output can be driven on the rising edge of the clock by
setting the configuration registers RCE bit to a 1. Using the
rising edge of clock for data reads may be beneficial to the
timing of some high-speed systems. The factory default
setting is the falling edge of SCK for standard SPI.
RCE=0 Read data is output on the falling edge of SCK
(Standard SPI).
RCE=1 Read data is output on the rising edge of SCK
(Fast SPI).
CF15:8
(RESERVED)
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
WR3
WR2
WR1
WR0
WD
RCE
HR1
HR0
WRITE PROTECT
RANGE
WRITE PROTECT
DIRECTION
READ DATA
CLOCK EDGE
HOLD-READY/BUSY
PIN FUNCTION
Figure 7. Configuration Register Bit Locations
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