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NX25F011B データシート(Datasheet) 6 Page - List of Unclassifed Manufacturers

部品番号. NX25F011B
部品情報  1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE
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6
NexFlash Technologies, Inc.
PRELIMINARY NXSF016F-1201
12/12/01 ©
NX25F011B
NX25F021B
NX25F041B
Table 1. Pin Descriptions
SI
Serial Data Input
SO
Serial Data Output
SCK
Serial Clock Input
CS
Chip Select Input
WP
Write Protect Input
Hold, R/B
Hold Input or Read Busy Output
Vcc
Power Supply
the SO pin will enter a high-impedance state and power
consumption will decrease to standby levels unless pro-
gramming is in process, in which case standby will resume
when programming is complete.
Write Protect (
WP
WP
WP
WP
WP)
The Write Protect input (
WP) works in conjunction with the
write protect range set in the configuration register bits.
When
WP is asserted (active low) the entire Flash memory
array is write protected. When high, any Flash memory
sector can be written to unless its address is within the write
protect range that is set in the configuration register.
Hold or Ready/Busy (
HOLD
HOLD
HOLD
HOLD
HOLD or R/B
B
B
B
B)
This multifunction pin can serve either as a Hold input
(
HOLD) or as a Ready-Busy output (R/B). The pin function
is user-programmable through the non-volatile configuration
register. Factory-programmed as a no-connect, the pin can
be reconfigured as a Ready-Busy output or as a Hold input
by setting the configuration register. See the configuration
register section of this data sheet for further details.
Power Supply Pins (Vcc and GND)
The NX25F011B, NX25F021B, and NX25F041B support
single power supply Read and Erase/Write operations in 5V
and 3V versions. Typical active power is as low as 2.5 mA
for the 3V version with standby current less than 1 µA.
Serial Data Input (SI)
The SPI bus Serial Data Input (SI) provides a means for data
to be written to (shifted into) the device.
Serial Data Output (SO)
The SPI bus Serial Data Output (SO) provides a means for
data to be read from (shifted out of) the device during a read
operation. When the device is deselected (
CS=1orHOLD=0)
the SO pin is in a high-impedance state.
Serial Clock (SCK)
All commands and data written to the Serial Input (SI) are
clocked relative to the rising edge of the Serial Clock (SCK).
All data read from the Serial Data Output (SO) is clocked
relative to the falling or rising edge of SCK as specified in
the non-volatile configuration register. The data output
clock edge is factory-programmed to the default condition
of the falling edge, allowing compatibility with standard SPI
systems. Clock rates of up to 20 MHz are supported.
Chip Select (
CS
CS
CS
CS
CS)
The NX25F011B, NX25F021B, and NX25F041B are
selected for operation when the Chip Select input (
CS) is
asserted low. SCK must be low when (
CS) is asserted to a
low state. Upon power-up, an initial low-to-high transition of
CS is required before any command sequence will be
acknowledged. The device can be deselected to a
non-active state when
CS isbroughthigh.Oncedeselected,
Figure 3B. NX25F011B, NX25F021B, and NX25F041B
Pin Assignments, 28-Pin TSOP (Type I)
HOLD-R/B
NC
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SI
SCK
Hold R/B
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
Figure 3A. NX25F011B and NX25F021B
Pin Assignments, 8-Pin SOIC
Figure 3C. NX25F041B
Pin Assignments, 28-Pin SOIC
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
WP
NC
HOLD-R/B
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
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9
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14
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