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AD9992 データシート(Datasheet) 5 Page - Analog Devices

部品番号. AD9992
部品情報  12-Bit CCD Signal Processor with Precision Timing Generator
ダウンロード  92 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9992
Rev. C | Page 5 of 92
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 40 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CDS
Allowable CCD Reset Transient
0.5
0.8
V
The limit is the lower of AVDD + 0.2 V or 2.2 V.
CDS Gain Accuracy
VGA gain = 6.3 dB (Code 15, default value).
−3.0 dB CDS Gain
−3.3
−2.8
−2.3
dB
0 dB CDS Gain
−0.5
0
+0.5
dB
+3 dB CDS Gain
2.4
2.9
3.4
dB
+6 dB CDS Gain
5.0
5.5
6.0
dB
Maximum Input Range Before Saturation
VGA gain = 6.3 dB (Code 15, default value).
−3 dB CDS Gain
1.4
V p-p
0 dB CDS Gain
1.0
V p-p
+3 dB CDS Gain
0.7
V p-p
+6 dB CDS Gain
0.5
V p-p
Allowable OB Pixel Amplitude (See
Figure 2)
0 dB CDS Gain (Default)
−100
+200
mV
+6 dB CDS Gain
−50
+100
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
1024
Steps
Gain Monotonicity
Guaranteed
Gain Range
Low Gain (VGA Code 15, Default)
6.3
dB
Maximum Gain (VGA Code 1023)
42.4
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
1024
Steps
Clamp Level
Measured at ADC output.
Minimum Clamp Level (Code 0)
0
LSB
Maximum Clamp Level (Code 1023)
255
LSB
ADC
Resolution
12
Bits
Differential Nonlinearity (DNL)
−1.0
±0.5
+1.0
LSB
No Missing Codes
Guaranteed
Integral Nonlinearity (INL)
1
4
LSB
Full-Scale Input Voltage
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
1.4
V
Reference Bottom Voltage (REFB)
0.4
V
SYSTEM PERFORMANCE
Includes entire signal chain.
Gain Accuracy
0 dB CDS gain.
Low Gain (VGA Code 15)
5.8
6.3
6.8
dB
Gain = (0.0358 × Code) + 5.76 dB.
Maximum Gain (VGA Code 1023)
41.9
42.4
42.9
dB
Peak Nonlinearity, 1.0 V Input Signal
0.1
0.2
%
6 dB VGA gain, 0 dB CDS gain applied.
Total Output Noise
0.5
LSB rms
AC-grounded input, 6 dB VGA gain applied.
Power Supply Rejection (PSR)
50
dB
Measured with step change on supply.




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