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AD9992 データシート(Datasheet) 78 Page - Analog Devices

部品番号. AD9992
部品情報  12-Bit CCD Signal Processor with Precision Timing Generator
ダウンロード  92 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9992
Rev. C | Page 78 of 92
Table 33. Memory Configuration and MODE Registers
Address
Data Bits
Default Value
Update Type
Mnemonic
Description
0x28
[4:0]
0
SCK
VPATNUM
Total number of V-pattern groups.
[9:5]
0
SEQNUM
Total number of V-sequences.
0x2A
[2:0]
0
SCK
MODE
Total number of fields in MODE.
0x2B
[4:0]
0
SCK
FIELD0
Selected first field in MODE.
[9:5]
0
FIELD1
Selected second field in MODE.
[14:10]
0
FIELD2
Selected third field in MODE.
[19:15]
0
FIELD3
Selected fourth field in MODE.
[24:20]
0
FIELD4
Selected fifth field in MODE.
0x2C
[4:0]
0
SCK
FIELD5
Selected sixth field in MODE.
[9:5]
0
FIELD6
Selected seventh field in MODE.
Table 34. Timing Core Registers
Address
Data Bits
Default
Value
Update
Type
Mnemonic
Description
0x30
[5:0]
0
SCK
H1POSLOC
H1 rising edge location.
[13:8]
20
H1NEGLOC
H1 falling edge location.
[16]
1
H1POL
H1 polarity control:
0: Inverse of Figure 19.
1: No inversion.
0x31
[5:0]
0
SCK
H2POSLOC
H2 rising edge location (H5 in HCLK Mode 3).
[13:8]
20
H2NEGLOC
H2 falling edge location (H5 in HCLK Mode 3).
[16]
1
H2POL
H2 polarity (H5 in HCLK Mode 3):
0: Inverse of Figure 19.
1: No inversion.
0x32
[5:0]
0
SCK
HLPOSLOC
HL rising edge location.
[13:8]
20
HLNEGLOC
HL falling edge location.
[16]
1
HLPOL
HL polarity control:
0: Inverse of Figure 19.
1: No inversion.
0x33
[5:0]
0
SCK
RGPOSLOC
RG rising edge location.
[13:8]
10
RGNEGLOC
RG falling edge location.
[16]
1
RGH2POL
RG polarity control:
0: Inverse of Figure 19.
1: No inversion.
0x34
[0]
0
SCK
H1HBLKRETIME
Retime H1, H2, HL HBLK to the internal clock:
0: No retime.
1: Retime.
[1]
0
H2HBLKRETIME
Recommended setting is retime enabled (1). Setting to 1
adds one cycle delay to programmed HBLK positions.
[2]
0
HLHBLKRETIME
[3]
0
HL_HBLK_EN
Enable HBLK for HL output:
0: Disable.
1: Enable.
[7:4]
4
HCLK_WIDTH
Enables wide H-clocks during HBLK interval. Set to 0 to
disable.
0x35
[2:0]
1
SCK
H1DRV
H1 drive strength:
0: Off.
1: 4.3 mA.
2: 8.6 mA.
3: 12.9 mA.
4: 4.3 mA.
5: 8.6 mA.
6: 12.9 mA.
7: 17.2 mA.




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