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AD9992 データシート(Datasheet) 3 Page - Analog Devices

部品番号. AD9992
部品情報  12-Bit CCD Signal Processor with Precision Timing Generator
ダウンロード  92 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9992
Rev. C | Page 3 of 92
SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
−25
+85
°C
Storage
−65
+150
°C
POWER SUPPLY VOLTAGE INPUTS
AVDD (AFE Analog Supply)
1.6
1.8
2.0
V
TCVDD (Timing Core Supply)
1.6
1.8
2.0
V
CLIVDD (CLI Input Supply)
1.6
3.0
3.6
V
RGVDD (RG, HL Driver)
2.7
3.0
3.6
V
HVDD1/HVDD2 (H1 to H8 Drivers)1
2.7
3.0
3.6
V
DVDD (Digital Logic)
1.6
1.8
2.0
V
DRVDD (Parallel Data Output Drivers)
1.6
3.0
3.6
V
IOVDD (Digital I/O)
1.6
3.0
3.6
V
XVVDD (Vertical Output Drivers)
1.6
3.0
3.6
V
CP1P8 (CP Supply Input)
1.6
1.8
2.0
V
LDOIN (LDO Supply Input)
2.25
3.0
3.6
V
POWER SUPPLY CURRENTS—40 MHz OPERATION
AVDD (1.8 V)
27
mA
TCVDD (1.8 V)
5
mA
CLIVDD (3 V)
1.5
mA
RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load)
10
mA
HVDD1/HVDD2 (3.3 V, 480 pF Total Load on H1 to H8)1
59
mA
DVDD (1.8 V)
9.5
mA
DRVDD (3 V, 10 pF Load on Each DOUT Pin)
6
mA
IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O)
2
mA
XVVDD (3 V, Depends on Load and Output Frequency of XV Signals)
2
mA
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Standby1 Mode
12
mA
Standby2 Mode
5
mA
Standby3 Mode
1.5
mA
MAXIMUM CLOCK RATE (CLI)
40
MHz
1 The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation
Total HVDD Power = [CL × HVDD × Pixel Frequency] × HVDD
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CL is the total capacitance seen by all H-outputs.




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