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CS5308 データシート(PDF) 11 Page - ON Semiconductor

部品番号 CS5308
部品情報  Two?뭁hase PWM Controller with Integrated Gate Drivers for VRM 8.5
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5308 データシート(HTML) 11 Page - ON Semiconductor

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CS5308
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11
APPLICATIONS INFORMATION
Overview
The CS5308 DC/DC controller from ON Semiconductor
was developed using the Enhanced V2 topology to meet
requirements of low voltage, high current loads with fast
transient requirements. Enhanced V2 combines the original
V2 topology with peak current−mode control for fast
transient response and current sensing capability. The
addition of an internal PWM ramp and implementation of
fast−feedback directly from VCORE has improved transient
response and simplified design. The CS5308 includes VTT
monitoring, VTTPGD, PWRGD, and MOSFET gate drivers
to provide a “fully integrated solution” to simplify design,
minimize circuit board area, and reduce overall system cost.
Two advantages of a multi−phase converter over a
single−phase converter are current sharing and increased
apparent output frequency. Current sharing allows the designer
to use less inductance in each phase than would be required
in a single−phase converter. The smaller inductor will
produce larger ripple currents but the total per phase power
dissipation is reduced because the RMS current is lower.
Transient response is improved because the control loop will
measure and adjust the current faster in a smaller output
inductor. Increased apparent output frequency is desirable
because the off− time and the ripple voltage of the two−phase
converter will be less than that of a single−phase converter.
Fixed Frequency Multi−Phase Control
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The CS5308 controller uses two−phase, fixed frequency,
Enhanced V2 architecture to measure and control currents in
individual phases. Each phase is delayed 180° from the
previous phase. Normally, GATE(H) transitions to a high
voltage at the beginning of each oscillator cycle. Inductor
current ramps up until the combination of the current sense
signal, the internal ramp and the output voltage ripple trip
the PWM comparator and bring GATE(H) low. Once
GATE(H) goes low, it will remain low until the beginning of
the next oscillator cycle. While GATE(H) is high, the
Enhanced V2 loop will respond to line and load variations.
On the other hand, once GATE(H) is low, the loop can not
respond until the beginning of the next PWM cycle.
Therefore, constant frequency Enhanced V2 will typically
respond to disturbances within the off−time of the converter.
The Enhanced V2 architecture measures and adjusts the
output current in each phase. An additional input (CSn) for
inductor current information has been added to the V2™ loop
for each phase as shown in Figure 9. The triangular inductor
current is measured differentially across RS, amplified by
CSA and summed with the Channel Startup Offset, the
Internal Ramp, and the Output Voltage at the non−inverting
input of the PWM comparator. The purpose of the Internal
Ramp is to compensate for propagation delays in the
CS5308. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation, and PWM duty cycles
above 50% without external slope compensation. As the
sum of the inductor current and the internal ramp increase,
the voltage on the positive pin of the PWM comparator rises
and terminates the PWM cycle. If the inductor starts a cycle
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The CS5308 provides a CSn
input for each phase, but the CSREF and COMP inputs are
common to all phases. Current sharing is accomplished by
referencing all phases to the same CSREF and COMP pins,
so that a phase with a larger current signal will turn off earlier
than a phase with a smaller current signal.


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