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MC68340 データシート(Datasheet) 30 Page - Freescale Semiconductor, Inc

部品番号. MC68340
部品情報  Integrated Processor with DMA User’s Manual
ダウンロード  441 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
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 30 page
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MC68340 USER’S MANUAL
MOTOROLA
memory system to signal the CPU32 or DMA when the transfer is complete and to note
the number of bits in the transfer. An external master can arbitrate for the bus using a
three-line handshaking interface.
1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of
processors is designed with the concept of providing maximum system safeguards.
System configuration and various monitors and timers are provided in the MC68340.
Power-on reset circuitry is a part of the SIM40. A bus monitor ensures that the system
does not lock up when there is no response to a memory access. The bus fault monitor
can reset the processor when a catastrophic bus failure occurs. Spurious interrupts are
detected and handled appropriately. A software watchdog can pull the processor out of an
infinite loop. An interrupt can be sent to the CPU32 with programmable regularity for
DRAM refresh, time-of-day clock, task switching, etc.
1.3.1.3 CLOCK SYNTHESIZER. The clock synthesizer generates the clock signals used
by all internal operations as well as a clock output used by external devices. The clock
synthesizer can operate with an inexpensive 32768-Hz watch crystal or an external
oscillator for reference, using an internal phase-locked loop and voltage-controlled
oscillator. At any time, software can select clock frequencies from 131 kHz to 16.78 MHz
or 25.16 MHz, favoring either low power consumption or high performance. Alternately, an
external clock can drive the clock signal directly at the operating frequency. With its fully
static HCMOS design, it is possible to completely stop the system clock without losing the
contents of the internal registers.
1.3.1.4 CHIP SELECT AND WAIT STATE GENERATION. Four programmable chip
selects provide signals to enable external memory and peripheral circuits, providing all
handshaking and timing signals with up to 175-ns access times with a 25-MHz system
clock (265 ns @ 16.78 MHz). Each chip select signal has an associated base address and
an address mask that determine the addressing characteristics of that chip select.
Address space and write protection can be selected for each. The block size can be
selected from 256 bytes up to 4 Gbytes in increments of 2n. Accesses can be preselected
for either 8- or 16-bit transfers. Fast synchronous termination or up to three wait states
can be programmed, whether or not the chip select signals are used. External
handshakes can also signal the end of a bus transfer. A system can boot from reset out of
8-bit-wide memory, if desired.
1.3.1.5 INTERRUPT HANDLING. Seven input signals are provided to trigger an external
interrupt, one for each of the seven priority levels supported. Seven separate outputs can
indicate the priority level of the interrupt being serviced. An input can direct the processor
to a default service routine, if desired. Interrupts at each priority level can be
preprogrammed to go to the default service routine. For maximum flexibility, interrupts can
be vectored to the correct service routine by the interrupting device.
1.3.1.6 DISCRETE I/O PINS. When not used for other functions, 16 pins can be
programmed as discrete input or output lines. Additionally, in other peripheral modules,
pins for otherwise unused functions can often be used for general input/output.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com




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