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MC68340 データシート(Datasheet) 42 Page - Freescale Semiconductor, Inc

部品番号. MC68340
部品情報  Integrated Processor with DMA User’s Manual
ダウンロード  441 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
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 42 page
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2- 8
MC68340 USER’S MANUAL
MOTOROLA
2.8.4 Read-Modify-Write Cycle (
RMC)
This output signal identifies the bus cycle as part of an indivisible read-modify-write
operation. It remains asserted during all bus cycles of the read-modify-write operation to
indicate that bus ownership cannot be transferred.
2.9 EXCEPTION CONTROL SIGNALS
These signals are used by the MC68340 to recover from an exception.
2.9.1 Reset (
RESET)
This active-low, open-drain, bidirectional signal is used to initiate a system reset. An
external reset signal (as well as a reset from the SIM40) resets the MC68340 and all
external devices. A reset signal from the CPU32 (asserted as part of the RESET
instruction) resets external devices; the internal state of the CPU32 is not affected. The
on-chip modules are reset, except for the SIM40. However, the module configuration
register for each on-chip module is not altered. When asserted by the MC68340, this
signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to Section 3
Bus Operation for a description of bus reset operation and Section 5 CPU32 for
information about the reset exception.
2.9.2 Halt (
HALT)
This active-low, open-drain, bidirectional signal is asserted to suspend external bus
activity, to request a retry when used with
BERR, or to perform a single-step operation. As
an output,
HALT indicates a double bus fault by the CPU32. Refer to Section 3 Bus
Operation for a description of the effects of
HALT on bus operation.
2.9.3 Bus Error (
BERR)
This active-low input signal indicates that an invalid bus operation is being attempted or,
when used with
HALT, that the processor should retry the current cycle. Refer to Section
3 Bus Operation for a description of the effects of
BERR on bus operation.
2.10 CLOCK SIGNALS
These signals are used by the MC68340 for controlling or generating the system clocks.
See Section 4 System Integration Module for more information on the various clocking
methods and frequencies.
2.10.1 System Clock (CLKOUT)
This output signal is the system clock output and is used as the bus timing reference by
external devices. CLKOUT can be varied in frequency or slowed in low power stop mode
to conserve power.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com




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