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MC68340 データシート(Datasheet) 11 Page - Freescale Semiconductor, Inc

部品番号. MC68340
部品情報  Integrated Processor with DMA User’s Manual
ダウンロード  441 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
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 11 page
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11/2/95
SECTION 1: OVERVIEW
UM Rev.1.0
x
MC68340 USER'S MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
5.6.1.3
On-Chip Hardware Breakpoint Overview.............................................5-64
5.6.2
Background Debug Mode...........................................................................5-65
5.6.2.1
Enabling BDM ...........................................................................................5-65
5.6.2.2
BDM Sources ............................................................................................5-66
5.6.2.2.1
External
BKPT Signal..........................................................................5-66
5.6.2.2.2
BGND Instruction ..................................................................................5-66
5.6.2.2.3
Double Bus Fault. .................................................................................5-66
5.6.2.3
Entering BDM ............................................................................................5-66
5.6.2.4
Command Execution................................................................................5-67
5.6.2.5
BDM Registers...........................................................................................5-67
5.6.2.5.1
Fault Address Register (FAR) .............................................................5-67
5.6.2.5.2
Return Program Counter (RPC) .........................................................5-67
5.6.2.5.3
Current Instruction Program Counter (PCC)....................................5-67
5.6.2.6
Returning from BDM.................................................................................5-68
5.6.2.7
Serial Interface..........................................................................................5-68
5.6.2.7.1
CPU Serial Logic..................................................................................5-69
5.6.2.7.2
Development System Serial Logic....................................................5-71
5.6.2.8
Command Set ...........................................................................................5-73
5.6.2.8.1
Command Format.................................................................................5-73
5.6.2.8.2
Command Sequence Diagram..........................................................5-74
5.6.2.8.3
Command Set Summary.....................................................................5-75
5.6.2.8.4
Read A/D Register (RAREG/RDREG)................................................5-76
5.6.2.8.5
Write A/D Register (WAREG/WDREG) ..............................................5-77
5.6.2.8.6
Read System Register (RSREG)........................................................5-77
5.6.2.8.7
Write System Register (WSREG).......................................................5-78
5.6.2.8.8
Read Memory Location (READ).........................................................5-79
5.6.2.8.9
Write Memory Location (WRITE)........................................................5-79
5.6.2.8.10
Dump Memory Block (DUMP). ...........................................................5-80
5.6.2.8.11
Fill Memory Block (FILL)......................................................................5-82
5.6.2.8.12
Resume Execution (GO)......................................................................5-83
5.6.2.8.13
Call User Code (CALL)........................................................................5-83
5.6.2.8.14
Reset Peripherals (RST)......................................................................5-85
5.6.2.8.15
No Operation (NOP).............................................................................5-85
5.6.2.8.16
Future Commands................................................................................5-86
5.6.3
Deterministic Opcode Tracking ..................................................................5-86
5.6.3.1
Instruction Fetch (IFETCH)......................................................................5-86
5.6.3.2
Instruction Pipe (
IPIPE)...........................................................................5-87
5.6.3.3
Opcode Tracking during Loop Mode ....................................................5-88
5.7
Instruction Execution Timing...........................................................................5-88
5.7.1
Resource Scheduling ..................................................................................5-88
5.7.1.1
Microsequencer ........................................................................................5-89
5.7.1.2
Instruction Pipeline...................................................................................5-89
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com




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