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MC68340 データシート(Datasheet) 14 Page - Freescale Semiconductor, Inc

部品番号. MC68340
部品情報  Integrated Processor with DMA User’s Manual
ダウンロード  441 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
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 14 page
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11/2/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68340 USER'S MANUAL
xiii
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
7.1.5
Comparison of Serial Module to MC68681 .............................................7-4
7.2
Serial Module Signal Definitions...................................................................7-4
7.2.1
Crystal Input or External Clock (X1) ..........................................................7-5
7.2.2
Crystal Output (X2) .......................................................................................7-5
7.2.3
External Input (SCLK)..................................................................................7-6
7.2.4
Channel A Transmitter Serial Data Output (TxDA).................................7-6
7.2.5
Channel A Receiver Serial Data Input (RxDA)........................................7-6
7.2.6
Channel B Transmitter Serial Data Output (TxDB).................................7-6
7.2.7
Channel B Receiver Serial Data Input (RxDB)........................................7-6
7.2.8
Channel A Request-To-Send (
RTSA) ......................................................7-6
7.2.8.1
RTSA...........................................................................................................7-6
7.2.8.2
OP0..............................................................................................................7-6
7.2.9
Channel B Request-To-Send (
RTSB).......................................................7-6
7.2.9.1
RTSB...........................................................................................................7-7
7.2.9.2
OP1..............................................................................................................7-7
7.2.10
Channel A Clear-To-Send (
CTSA) ...........................................................7-7
7.2.11
Channel B Clear-To-Send (
CTSB)............................................................7-7
7.2.12
Channel A Transmitter Ready (
T
≈RDYA).................................................7-7
7.2.12.1
T
≈RDYA......................................................................................................7-7
7.2.12.2
OP6..............................................................................................................7-7
7.2.13
Channel A Receiver Ready (
R
≈RDYA).....................................................7-7
7.2.13.1
R
≈RDYA......................................................................................................7-7
7.2.13.2
FFULLA.......................................................................................................7-7
7.2.13.3
OP4..............................................................................................................7-7
7.3
Operation............................................................................................................7-8
7.3.1
Baud Rate Generator ...................................................................................7-8
7.3.2
Transmitter and Receiver Operating Modes ............................................7-8
7.3.2.1
Transmitter .................................................................................................7-10
7.3.2.2
Receiver......................................................................................................7-11
7.3.2.3
FIFO Stack..................................................................................................7-12
7.3.3
Looping Modes .............................................................................................7-14
7.3.3.1
Automatic Echo Mode..............................................................................7-14
7.3.3.2
Local Loopback Mode .............................................................................7-14
7.3.3.3
Remote Loopback Mode .........................................................................7-14
7.3.4
Multidrop Mode .............................................................................................7-15
7.3.5
Bus Operation................................................................................................7-17
7.3.5.1
Read Cycles...............................................................................................7-17
7.3.5.2
Write Cycles...............................................................................................7-17
7.3.5.3
Interrupt Acknowledge Cycles................................................................7-17
7.4
Register Description and Programming .......................................................7-17
7.4.1
Register Description.....................................................................................7-17
7.4.1.1
Module Configuration Register (MCR)..................................................7-19
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com




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