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AD6624 データシート(Datasheet) 1 Page - Analog Devices

部品番号. AD6624
部品情報  Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD6624
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
REV. B
The AD6624 is part of Analog Devices’ SoftCell
® multicarrier
transceiver chipset designed for compatibility with Analog
Devices’ family of high sample rate IF sampling ADCs (AD6640/
AD6644 12- and 14-bit). The SoftCell receiver comprises a
digital receiver capable of digitizing an entire spectrum of
carriers and digitally selecting the carrier of interest for tuning
and channel selection. This architecture eliminates redundant
radios in wireless base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 30 dB or more. In addition, the programmable RAM
coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The AD6624 is compatible with standard ADC converters such
as the AD664x, AD9042, AD943x, and the AD922x families of
data converters. The AD6624 is also compatible with the AD6600
Diversity ADC, providing a cost and size reduction path.
Four-Channel, 80 MSPS Digital
Receive Signal Processor (RSP)
FUNCTIONAL BLOCK DIAGRAM
CH A
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
16 BITS
18 BITS
20 BITS
24 BITS
INA[13:0]
EXPA[2:0]
IENA
LIA-A
LIA-B
SYNCA
SYNCB
SYNCC
SYNCD
INB[13:0]
EXPB[2:0]
IENB
LIB-A
LIB-B
SDIN[3:0]
SDO[3:0]
DR[3:0]
SDFS[3:0]
SDFE[3:0]
SCLK[3:0]
MODE
DS(RD)
CS
RW (
WR)
DTACK(RDY)
A[2:0]
D[7:0]
CH B
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH C
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
CH D
NCO
rCIC2
RESAMPLER
CIC5
RAM
COEFFICIENT
FILTER
EXTERNAL SYNC
CIRCUITRY
JTAG
INTERFACE
BUILT-IN
SELF-TEST
FEATURES
80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI)
Dual High Speed Data Input Ports
Four Independent Digital Receivers in Single Package
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User-Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136,
EDGE, PHS, IS95
Micro and Pico Cell Systems
Wireless Local Loop
Smart Antenna Systems
Software Radios
In-Building Wireless Telephony
PRODUCT DESCRIPTION
The AD6624 is a four-channel (quad) digital receive signal
processor (RSP) with four cascaded signal-processing elements:
a frequency translator, two fixed-coefficient decimating filters,
and a programmable-coefficient decimating filter.




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