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AD6624 データシート(Datasheet) 13 Page - Analog Devices

部品番号. AD6624
部品情報  Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
ダウンロード  40 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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 13 page
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REV. B
AD6624
–13–
ARCHITECTURE
The AD6624 has four signal processing stages: a Frequency
Translator, second order Resampling Cascaded Integrator
Comb FIR filters (rCIC2), a fifth order Cascaded Integrator
Comb FIR filter (CIC5), and a RAM Coefficient FIR filter
(RCF). Multiple modes are supported for clocking data into and
out of the chip, and provide flexibility for interfacing to a wide
variety of digitizers. Programming and control is accomplished
via serial and microprocessor interfaces.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into in-phase (I) and quadrature (Q)
components. This stage translates the input signal from a digital
intermediate frequency (IF) to digital baseband. Phase and
amplitude dither may be enabled on-chip to improve spurious
performance of the NCO. A phase-offset word is available to
create a known phase relationship between multiple AD6624s or
between channels.
Following frequency translation is a resampling, fixed-coefficient,
high speed, second order, Resampling Cascade Integrator
Comb (rCIC2) filter that reduces the sample rate based on the
ratio between the decimation and interpolation registers.
The next stage is a fifth order Cascaded Integrator Comb (CIC5)
filter whose response is defined by the decimation rate. The
purpose of these filters is to reduce the data rate to the final
filter stage so it can calculate more taps per output.
The final stage is a sum-of-products FIR filter with program-
mable 20-bit coefficients, and decimation rates programmable
from 1 to 256 (1–32 in practice). The RAM Coefficient FIR
filter (RCF in the Functional Block Diagram) can handle a
maximum of 160 taps.
The overall filter response for the AD6624 is the composite of
all decimating and interpolating stages. Each successive filter
stage is capable of narrower transition bandwidths but requires
a greater number of CLK cycles to calculate the output. More
decimation in the first filter stage will minimize overall power
consumption. Data from the chip is interfaced to the DSP via a
high-speed synchronous serial port.
Figure 18a illustrates the basic function of the AD6624: to
select and filter a single channel from a wide input spectrum.
The frequency translator “tunes” the desired carrier to baseband.
Figure 18b shows the combined filter response of the rCIC2,
CIC5, and RCF.
SIGNAL OF INTEREST
fS/2
WIDEBAND INPUT SPECTRUM (–
fSAMP/2 TO fSAMP/2)
SIGNAL OF INTEREST “IMAGE”
–3
fS/8
–5
fS/16
fS/4
–3
fS/16
fS/8
fS/16
DC
fS/16
fS/8
3
fS/16
fS/4
5
fS/16
3
fS/8
fS/2
WIDEBAND INPUT SPECTRUM (e.g., 30MHz FROM HIGH-SPEED ADC)
AFTER FREQUENCY TRANSLATION
NCO “TUNES” SIGNAL TO BASEBAND
FREQUENCY TRANSLATION (e.g., SINGLE 1MHz CHANNEL TUNED TO BASEBAND)
fS/2
–3
fS/8
–5
fS/16
fS/4
–3
fS/16
fS/8
fS/16
DC
fS/16
fS/8
3
fS/16
fS/4
5
fS/16
3
fS/8
fS/2
Figure 18a. Frequency Translation of Wideband Input Spectrum
kHz
10
–1000
1000
–800 –600 –400 –200
0
200
400
600
800
0
–50
–20
–40
–10
–30
–60
0
–80
–100
–70
–90
–110
–120
–140
–130
–150
Figure 18b. Composite Filter Response of rCIC2, CIC5, and RCF




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