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P89LPC9401 データシート(PDF) 20 Page - NXP Semiconductors |
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P89LPC9401 データシート(HTML) 20 Page - NXP Semiconductors |
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20 / 59 page  P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01 — 5 September 2005 20 of 59 Philips Semiconductors P89LPC9401 8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver • CODE 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9401 has 8 kB of on-chip Code memory. 7.11 Data RAM arrangement The 768 bytes of on-chip RAM are organized as shown in Table 5. 7.12 Interrupts The P89LPC9401 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC9401 supports 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, and SPI. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 7.12.1 External interrupt inputs The P89LPC9401 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC9401 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.15 “Power reduction modes” for details. Table 5: On-chip data memory usages Type Data RAM Size (bytes) DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 |
同様の部品番号 - P89LPC9401 |
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同様の説明 - P89LPC9401 |
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