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AD9923A データシート(Datasheet) 4 Page - Analog Devices

部品番号. AD9923A
部品情報  CCD Signal Processor with V-Driver and Precision Timing™ Generator
ダウンロード  88 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9923A
Rev. 0 | Page 4 of 88
DIGITAL SPECIFICATIONS
DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
VIH
2.1
V
Low Level Input Voltage
VIL
0.6
V
High Level Input Current
IIH
10
μA
Low Level Input Current
IIL
10
μA
Input Capacitance
CIN
10
pF
LOGIC OUTPUTS
Powered by DVDD, DRVDD
High Level Output Voltage
At IOH = 2 mA
VOH
DVDD − 0.5, DRVDD − 0.5
V
Low Level Output Voltage
At IOL = 2 mA
VOL
0.5
V
H-DRIVER SPECIFICATIONS
HVDD = RGVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
RG and H-DRIVER OUTPUTS
RG, HL, and H1 to H4 powered by RGVDD, HVDD
High Level Output Voltage
At maximum current
RGVDD − 0.5, HVDD − 0.5
V
Low Level Output Voltage
At maximum current
0.5
V
Maximum Output Current
Programmable
30
mA
Maximum Load Capacitance
For each output
100
pF
VERTICAL DRIVER SPECIFICATIONS
VDD1 = VDD2 = 3.3 V, VH1 = VH2 = 15 V, VM1 = VM2 = VMM = 0 V, VL1 = VL2 = VLL = −7.5 V, 25°C.
Table 4.
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
V-DRIVER OUTPUTS
Simplified load conditions, 3000 pF to ground
Delay Time
VL to VM and VM to VH
Rising edges
tPLM, tPMH
35
ns
VM to VL and VH to VM
Falling edges
tPML, tPHM
35
ns
Rise Time
VL to VM
tRLM
125
ns
VM to VH
tRMH
260
ns
Fall Time
VM to VL
tFML
220
ns
VH to VM
tFHM
125
ns
Output Currents
@ −7.25 V
+10
mA
@ −0.25 V
−22
mA
@ +0.25 V
+22
mA
@ +14.75 V
−10
mA
RON
35
Ω
SUBCK OUTPUT
Simplified load conditions, 1000 pF to ground
Delay Time
VLL to VH
tPLH
25
ns
VH to VLL
tPHL
30
ns
VLL to VMM
tPLM
25
ns




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