AD9923ABBCZ datasheet(57/88 Pages) AD

部品番号	AD9923ABBCZ

部品情報	CCD Signal Processor with V-Driver and Precision Timing??Generator

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AD9923A

Rev. 0 | Page 57 of 88

Optical Black Clamp

The optical black clamp loop removes residual offsets in the

signal chain and tracks low frequency variations in the CCD

black level. During the optical black (shielded) pixel interval on

each line, the ADC output is compared with a fixed black level

reference, selected by the user in the CLAMPLEVEL register.

The value can be programmed between 0 LSB and 255 LSB in

1023 steps. The resulting error signal is filtered to reduce noise

and the correction value is applied to the ADC input through a

DAC. Normally, the optical black clamp loop is turned on once

per horizontal line, but this loop can be updated more slowly to

suit a particular application. If external digital clamping is used

during postprocessing, the AD9923A optical black clamping

can be disabled using the CLPENABLE register (Address 0x00,

Bit D2). Even though the loop is disabled, the CLAMPLEVEL

register can still be used to provide programmable offset

adjustment.

The CLPOB pulse should be placed during the CCD optical

black pixels. It is recommended that the CLPOB pulse duration

is at least 20 pixels wide to minimize clamping noise. Shorter

pulse widths can be used, but clamping noise might increase,

reducing the ability to track low frequency variations in the

black level. See the Horizontal Clamping and Blanking section

for timing examples.

Digital Data Outputs

The digital output data is latched using the DOUTPHASE

register value, as shown in Figure 73. Output data timing is shown

in Figure 21 and Figure 22. It is also possible to leave the output

latches transparent, so that the data outputs from the ADC are

immediately valid. Programming the DOUTLATCH register,

Bit D1 to 1 sets the output latches transparent. The data outputs

can also be disabled (three-stated) by setting the DOUTDISABLE

Register 0x01, Bit D0 to 1.

The DCLK output can be used for external latching of the data

outputs. By default, the DCLK output tracks the value of the

DOUTPHASE register. By changing the DCLKMODE register,

the DCLK output can be held at a fixed phase, and the

DOUTPHASE register value is ignored.

To optimize the delay between the DCLK rising edge and the

data output transition, the DOUTDELAY register is used. By

default, there is approximately 8 ns of delay from the rising edge

of DCLK to the transition of the data outputs. See the High

Speed Timing Generation section for more information.

Switching the data outputs can couple noise into the analog

signal path. To minimize switching noise, set the DOUTPHASE

register to the same edge as the SHP sampling location, or up to

11 edges after the SHP sampling location. Other settings can

produce good results, but require experimentation. It is

recommended that the DOUTPHASE location not occur

between the SHD sampling location and 11 edges after the SHD

location. For example, if SHDLOC = 0, set DOUTPHASE to an

edge location of 12 or greater. If adjustable phase is not required

for the data outputs, the output latch can be left transparent

using Register 0x01, Bit D1.

Data output coding is normally straight binary, but can be

changed to gray coding by setting the GRAYEN Register 0x01,

Bit D2 to 1.

同様の部品番号 - AD9923ABBCZ

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