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AD9927 データシート(Datasheet) 81 Page - Analog Devices

部品番号. AD9927
部品情報  14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
ダウンロード  100 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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 81 page
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AD9927
Rev. 0 | Page 81 of 100
EXTERNAL RESET IN
B6
A7
B7
A8
B8
A9
B9
A10
A2
K12
H12
J8
J7
K8
E10
A1
J12
J6
A11
A12
B10
B12
C6
C9
C12
D9
D12
E9
E12
IOVDD
IOVSS
XVVDD
DVSS
(LSB) D0
D1
D2
D3
D4
D5
D6
AVSS
TCVSS
RGVSS
D7
D8
L8
C10
M6
L4
G2
K2
E11
C2
H4
H3
H2
H1
LDOVSS
CPVSS
8
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE V5V (PIN E10) THROUGH DIODE
18
3
14
DATA OUTPUTS
DCLK OUTPUT
H1, H2 TO CCD
H3, H4 TO CCD
H7, H8 TO CCD
H5, H6 TO CCD
SERIAL INTERFACE
(FROM ASIC/DSP)
0.1µF
0.1µF
ANALOG OUTPUT FROM CCD
0.1µF
RG TO CCD
HL TO CCD
AD9927BBCZ
NOT DRAWN TO SCALE
EXTERNAL SYNC IN
VERTICAL SYNC IN/OUT
HORIZONTAL SYNC IN/OUT
0.1µF
+3V CP OUTPUT
VH SUPPLY
VL SUPPLY
SUBCK OUTPUT (TO CCD)
VERTICAL OUTPUT (TO CCD)
+1.8V SUPPLY
TEST1
TEST3
V5V
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
TEST4
TEST5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1.0µF
25V
4.7µF
10V
0.1µF
10V
0.1µF
25V
HVSS2
HVSS1
DRVSS
0.1µF
DRVDD
0.1µF
J1
H2
G1
F2
MASTER CLOCK INPUT (3V LOGIC)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
A6
F12
NC
TEST2
TEST6
D10
G9
J9
TEST0
H6
H5
K1
J2
NC
G12
GPO OUTPUT
(SEE POWER-UP
PROCEDURE)
CLIVDD
L5
E2
F10
F1
E1
F9
D2
D1
C1
B2
B1
B11
L6
L7
M4
LDOIN
LDOOUT
SENSE
LDO1P8EN
LDO3P2EN
CPCLI
CP1P8
CPFCB
CPFCT
CP3P3
+1.8V CLI SUPPLY
H1
L1
DVDD
+1.8V SUPPLY
+3V CP OUTPUT
AVDD
TCVDD
RGVDD
HVDD1
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
4.7µF
6.3V
HVDD2
0.1µF
+1.8V CP INPUT
0.1µF
3.3µF
+3V CP OUTPUT
+3V CP OUTPUT
Figure 95. Typical 1.8 V Circuit Configuration Using Charge Pump for HVDD and RGVDD
5pF ~ 20pF
5pF ~ 20pF
CLI
CLO
AD9927
24MHz TO 36MHz
XTAL
2MΩ
0Ω ~ 500Ω
375Ω
K7
K6
Figure 96. Crystal Application Using CLI/CLO (Consult Crystal Data Sheet for Component Values)




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