AD9927 datasheet(92/100 Pages) AD

部品番号	AD9927

部品情報	14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator

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AD9927

Rev. 0 | Page 92 of 100

Address

Data

Bits

Default

Value

Update

Type

Name

Description

A6

[12:0]

0

VD

GP8_TOG2_LN

General-Purpose Signal 8, second toggle position, line location.

[25:13]

0

GP8_TOG2_PX

General-Purpose Signal 8, second toggle position, pixel location.

A7

[12:0]

0

VD

GP8_TOG3_FD

General-Purpose Signal 8, third toggle position, field location.

[25:13]

0

GP8_TOG3_LN

General-Purpose Signal 8, third toggle position, line location.

A8

[12:0]

0

VD

GP8_TOG3_PX

General-Purpose Signal 8, third toggle position, pixel location.

[25:13]

0

GP8_TOG4_FD

General-Purpose Signal 8, fourth toggle position, field location.

A9

[12:0]

0

VD

GP8_TOG4_LN

General-Purpose Signal 8, fourth toggle position, line location.

[25:13]

0

GP8_TOG4_PX

General-Purpose Signal 8, fourth toggle position, pixel location.

AA

[0]

0

VD

SUBCK_TOG1_13

Bit [13] for SUBCK Toggle Position 1. For 14-bit H-counter mode.

[1]

0

VD

SUBCK_TOG2_13

Bit [13] for SUBCK Toggle Position 2. For 14-bit H-counter mode.

[2]

0

VD/SG

SUBCKHP_TOG1_13

Bit [13] for SUBCK HP Toggle 1. For 14-bit H-counter mode.

[3]

0

VD/SG

SUBCKHP_TOG2_13

Bit [13] for SUBCK HP Toggle 2. For 14-bit H-counter mode.

Table 57. Update Control Registers

Address

Data

Bits

Default Value

Update

Name

Description

B0

[15:0]

1803

SCK

AFE_UPDT_SCK

Each bit corresponds to one address location.

AFE_UPDT_SCK [0] = 1, update Address 0x00 on SL rising edge.

AFE_UPDT_SCK [1] = 1, update Address 0x01 on SL rising edge.

…

AFE_UPDT_SCK [15] = 1, update Address 0x0F on SL rising edge.

B1

[15:0]

E7FC

SCK

AFE_UPDT_VD

Each bit corresponds to one address location.

AFE_UPDT_VD [0] = 1, update Address 0x00 on VD rising edge.

AFE_UPDT_VD [1] = 1, update Address 0x01 on VD rising edge.

…

AFE_UPDT_VD [15] = 1, update Address 0x0F on VD rising edge.

B2

[15:0]

F8FD

SCK

MISC_UPDT_SCK

Enable SCK update of miscellaneous registers,

Address 0x10 to Address 0x1F.

B3

[15:0]

0702

SCK

MISC_UPDT_VD

Enable VD update of miscellaneous registers,

Address 0x10 to Address 0x1F.

B4

[15:0]

FFF9

SCK

VDHD_UPDT_SCK

Enable SCK update of VDHD registers, Address 0x20 to Address 0x2F.

B5

[15:0]

0006

SCK

VDHD_UPDT_VD

Enable VD update of VDHD registers, Address 0x20 to Address 0x2F.

Table 58. Extra Registers

Address

Data Bits

Default Value

Update

Name

Description

D4

[0]

0

SCK

TEST

Test use only. Set to 0.

[1]

0

GPO_INT_EN

Allow observation of internal signals at GPO5 to GPO8 outputs.

GPO5: OUTCONTROL.

GPO6: HBLK.

GPO7: CLPOB.

GPO8: PBLK.

[9:2]

0

TEST

Test use only. Set to 0.

D7

[0]

0

SCK

TEST

Test use only. Set to 0.

[1]

0

XV24_SWAP

Set to 1 to change the V-driver output configuration so that XV15 is

output on the XV24 output pin. Useful with special vertical

sequence alternation mode when the XV24 register is reserved for

pattern selection.

D8

[27:0]

0

SCK

START

Recommended start-up register. Should be set to 0x888.

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