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AD9923ABBCZRL データシート(PDF) 18 Page - Analog Devices |
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AD9923ABBCZRL データシート(HTML) 18 Page - Analog Devices |
18 / 88 page AD9923A Rev. 0 | Page 18 of 88 HORIZONTAL CLAMPING AND BLANKING The AD9923A horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual controls are provided for CLPOB, PBLK, and HBLK during different regions of each field. This allows dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts. Individual CLPOB and PBLK Patterns The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 23. These two signals are independently programmed using the registers in Table 11. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the first and second toggle positions of the pulse. Both signals are active low and should be programmed accordingly. A separate pattern for CLPOB and PBLK can be programmed for each V-sequence. As described in the Vertical Timing Generation section, several V-sequences can be created, each containing a unique pulse pattern for CLPOB and PBLK. Figure 46 shows how the sequence change positions divide the readout field into regions. A different V-sequence can be assigned to each region, allowing the CLPOB and PBLK signals to change with each change in the vertical timing. Unused CLPOB and PBLK toggle positions should be set to 8191. CLPOB and PBLK Masking Area The AD9923A allows the CLPOB and/or PBLK signals to be disabled during certain lines in the field without changing the existing CLPOB and/or PBLK pattern settings. To use CLPOB masking, the CLPMASKSTART and CLPMASKEND registers are programmed to specify the starting and ending lines in the field where the CLPOB patterns are ignored. There are three sets of CLPMASKSTART and CLPMASKEND registers, allowing up to three CLPOB masking areas to be created. CLPOB masking registers are not specific to a given V-sequence; they are active for any existing field of timing. To disable the CLPOB masking feature, set these registers to the maximum value, 0xFFF (default value). To use PBLK masking, the PBLKMASKSTART and PBLKMASKEND registers are programmed to specify the starting and ending lines in the field where the PBLK patterns are ignored. There are three sets of PBLKMASKSTART and PBLKMASKEND registers, allowing the creation of up to three PBLK masking areas. PBLK masking registers are not specific to a given V-sequence; they are active for any existing field of timing. To disable the PBLK masking feature, set these registers to the maximum value, 0xFFF (default value). Table 11. CLPOB and PBLK Pattern Registers Register Length (Bits) Range Description CLPOBPOL 1 High/low Starting polarity of CLPOB for each V-sequence PBLKPOL 1 High/low Starting polarity of PBLK for each V-sequence CLPOBTOG1 13 0 to 8191 pixel location First CLPOB toggle position within the line for each V-sequence CLPOBTOG2 13 0 to 8191 pixel location Second CLPOB toggle position within the line for each V-sequence PBLKTOG1 13 0 to 8191 pixel location First PBLK toggle position within the line for each V-sequence PBLKBTOG2 13 0 to 8191 pixel location Second PBLK toggle position within the line for each V-sequence CLPMASKSTART 12 0 to 4095 line location CLPOB masking area—starting line within the field (maximum of three areas) CLPMASKEND 12 0 to 4095 line location CLPOB masking area—ending line within the field (maximum of three areas) PBLKMASKSTART 12 0 to 4095 line location PBLK masking area—starting line within the field (maximum of three areas) PBLKMASKEND 12 0 to 4095 line location PBLK masking area—ending line within the field (maximum of three areas) 3 2 1 HD CLPOB PBLK PROGRAMMABLE SETTINGS: 1START POLARITY (CLAMP AND BLANK REGIONS ARE ACTIVE LOW). 2FIRST TOGGLE POSITION. 3SECOND TOGGLE POSITION. ACTIVE ACTIVE Figure 23. Clamp and Preblank Pulse Placement |
同様の部品番号 - AD9923ABBCZRL |
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同様の説明 - AD9923ABBCZRL |
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