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AD9942 データシート(Datasheet) 14 Page - Analog Devices

部品番号. AD9942
部品情報  Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing™ Core
ダウンロード  36 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9942
Rev. A | Page 14 of 36
SYSTEM OVERVIEW
CCD
SERIAL
INTERFACE
DOUT
DIGITAL IMAGE
PROCESSING
ASIC
V DRIVER
HD_A, VD_A,
HD_B, VD_B
CLI_A, CLI_B
V1 > Vx, VSG1 > VSGx, SUBCK
H1A TO H4A, RG_A
H1B TO H4B, RG_B
AD9942
INTEGRATED
AFE + TD
CCDIN_A
CCDIN_B
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
Figure 11. Typical Application
Figure 12. Vertical and Horizontal Counters
Figure 11 shows the typical system application diagram for the
AD9942. The CCD output is processed by the AD9942 AFE
circuitry, which consists of a CDS, a VGA, a CLPOB, and an
ADC. The digitized pixel information is sent to the digital
image processor chip, where all postprocessing and
compression occurs. To operate the CCD, CCD timing param-
eters are programmed from the image processor to the AD9942
through the 6-wire serial interface. From the system master
clock, CLI, which is provided by the image processor, the device
generates the high speed CCD clocks and internal AFE clocks.
All AD9942 clocks are synchronized with VD_X and HD_X.
The CLPOB is programmed and generated internally.
The H drivers for H1A to H4A, H1B to H4B, RG_A, and RG_B
are included in the AD9942, allowing these clocks to be directly
connected to the CCD. An H driver voltage of 3 V is supported
in the AD9942.
Figure 12 shows the horizontal and vertical counter dimensions
for the device. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
VD_X
HD_X
CLI_X
MAX HD LENGTH IS 4095 PIXELS
MAX VD LENGTH IS 4095 LINES
Figure 13. Maximum VD_X/HD_X Dimensions




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