AD9942

Rev. A | Page 16 of 36

COMPLETE REGISTER LISTING

In Table 8 through Table 16, note the following:

•

All addresses and default values are expressed in hexadecimal format.

•

All registers are VD_X/HD_X updated as shown in Figure 14, except for the registers indicated in Table 8, which are SL_X updated.

•

Each channel is programmed independently using the 5-wire serial interface. Both channels can be programmed with the same

register values by tying the SL_A and SL_B signals together and the SDATA_A and SDATA_B signals together.

Table 8. Updated Registers upon Rising Edge of SL_X

Register

Description

OPRMODE

AFE operation modes

CTLMODE

AFE control modes

SW_RESET

Software reset bit

TGCORE _RSTB

Reset bar signal for internal TG core

PREVENTUPDATE

Prevents update of registers

VDHDEDGE

VD/HD active edge

FIELDVAL

Resets internal field pulse

HBLKRETIME

Retimes the HBLK to internal clock

H1CONTROL

H1 polarity control

RGCONTROL

RG signal control polarity

DRVCONTROL

Drive-strength control

SAMPCONTROL

SHP/SHD sample control

DOUTPHASE

DOUT phase control

Table 9. CHN_A and CHN_B AFE Register Map

Address

Data Bit Content

Default (Hex)

Name

Description

00

[11:0]

4

OPRMODE

AFE operation modes (see Table 15).

01

[9:0]

0

TESTMODE

Internal test mode. Should always be set = 0.

02

[7:0]

80

CLAMP LEVEL

CLPOB level.

03

[11:0]

4

CTLMODE

AFE control modes (see Table 16).

04

[17:0]

0

TESTMODE

Test operation only. Set = 0.

05

[17:0]

0

TESTMODE

Test operation only. Set = 0.

Table 10. CHN_A and CHN_B Miscellaneous Register Map

Address

Data Bit Content

Default (Hex)

Name

Description

10

[0]

0

SW_RST

Software reset.1 = reset all registers to default, then self-clear back to 0.

11

[0]

0

OUT_CONTROL

Output control. 0 = make all dc outputs inactive.

12

[0]

0

TGCORE_RSTB

Timing core reset bar. 0 = reset TG core; 1 = resume operation.

13

[11:0]

0

UPDATE

Serial update. Sets the line (HD) within the field to update serial data.

14

[0]

0

PREVENTUPDA

TE

Prevents the update of the VD-updated registers. 1 = prevent update.

15

[0]

0

VDHDEDGE

VD/HD active edge.

0 = falling edge triggered; 1 = rising edge triggered.

16

[1:0]

0

FIELDVAL

Field value sync.

0 = next field 0; 1 = next field 1; 2/3 = next field 2.

17

[0]

0

HBLKRETIME

Retime HBLK to internal H1 clock. Preferred setting is 1. Setting to 1 adds

one cycle delay to HBLK toggle positions.

18

[1:0]

0

TEST MODE

Internal test mode. Should always be set = 0.

19

[0]

0

TEST MODE

Internal test mode. Should always be set = 0.

1A

[0]

0

TEST MODE

Internal test mode. Should always be set = 0.

E8

[2:0]

TEST MODE

Internal test mode. Should always be set = 0.

[11:3]

0

VGAGAIN

VGA gain control.