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AD9889BBSTZ-165 データシート(PDF) 7 Page - Analog Devices |
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AD9889BBSTZ-165 データシート(HTML) 7 Page - Analog Devices |
7 / 12 page Preliminary Technical Data AD9889B Rev. PrA | Page 7 of 12 A B C D E F G J H K 10 8 7 6 3 2 1 95 4 BOTTOM VIEW (Not to Scale) Figure 4. 76-Ball BGA Configuration (Top View) Table 3. Pin Function Descriptions Pin No. BGA LFCSP LQFP Mnemonic Type1 Description A1 to A10, B1 to B10, C9, C10, D9, D10 39 to 47, 50 to 63, 2 50 to 58, 65 to 78, 2 D[23:0] I Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V. D1 6 6 CLK I Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V. C2 3 3 DE I Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V. C1 4 4 HSYNC I Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. D2 5 5 VSYNC I Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. J3 18 23 EXT_SW I Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground. K3 20 25 HPD I Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to 5.0 V CMOS logic level. E2 7 7 S/PDIF I S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V. E1 8 8 MCLK I Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level. F2, F1, G2, G1 9 to 12 9 to 12 I2S[3:0] I I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V. H2 13 13 SCLK I I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. H1 14 14 LRCLK I Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V. J72 262 332 PD/A0 I Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the PD/A0 pin state when the supplies are applied to the AD9889B. 1.8 V to 3.3 V CMOS logic level. K1, K2 21, 22 27, 28 TxC−/TxC+ O Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level. K10, J10 30, 31 37, 38 Tx2−/Tx2+ O Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS logic level. K7, K8 27, 28 34, 35 Tx1−/Tx1+ O Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate; TMDS logic level. K4, K5 24, 25 30, 31 Tx0−/Tx0+ O Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS logic level. H10 32 40 INT O Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended. J2, J5, J8, K9 19, 23, 29 24, 29, 36, 41 AVDD P 1.8 V Power Supply for TMDS Outputs. |
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同様の説明 - AD9889BBSTZ-165 |
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