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MC141541 データシート(PDF) 8 Page - Motorola, Inc |
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MC141541 データシート(HTML) 8 Page - Motorola, Inc |
8 / 16 page MC141541 MOTOROLA 8 REGISTERS Display Register 0 1 2 3 4 5 6 7 CCS0 CRADDR Bit 7 CCS0 — This bit defines a specific character color out of the two preset colors. Color 1 is selected if this bit is cleared, and Color 2 otherwise. Bit 6–0 CRADDR — These seven bits address the 128 characters or symbols residing in the character ROM. Row Control Registers Coln 30 0 1 2 3 4 5 6 7 CWS CHS B2 G2 R2 B1 G1 R1 COLN 30 Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color 2 by R2, G2, and B2. Bit 1 CHS — This bit determines the height of a display symbol. When it is set, the symbol is displayed in double height. Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the character is displayed in double width. Coln 31 0 1 2 3 4 5 6 7 B4 G4 R4 B3 G3 R3 COLN 31 Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color 4 by R4, G4, and B4. Window 1 Registers Row 10 Coln 0 0 1 2 3 4 5 6 7 ROW END ADDR MSB LSB ROW START ADDR MSB LSB COLN 0 ROW 10 Row 10 Coln 1 WEN CCS1 COL START ADDR MSB LSB COLN 1 0 1 2 3 4 5 6 7 ROW 10 HPOL Bit 2 WEN — This bit enables the background Window 1 generation when it is set. Bit 1 CCS1 — This additional color select bit provides the characters residing within Window 1 with two extra color selections, making a total of four selections for that row. Bit 0 HPOL — This bit selects the polarity of the incoming horizontal sync signal (HFLB) on Pin 5. If it is negative polar- ity, clear this bit. Otherwise, set this bit to 1 to represent the positive H sync signal. After power–on, this bit is cleared. Row 10 Coln 2 RG COL END ADDR MSB LSB COLN 2 0 1 2 3 4 5 6 7 B ROW 10 Bits 2–0 R, G and B — These bits control the color of Win- dow 1. Window 1 occupies Columns 0–2 of Row 10; Window 2 occupies Columns 3–5; and Window 3 occupies Columns 6–8. Window 1 has the highest priority, and Window 3 the least. If window overlapping occurs, the higher priority win- dow will cover the lower one, and the higher priority color will take over on the overlap window area. If the start address is greater than the end address, this window will not be dis- played. Window 2 Registers Row 10 Coln 3 0 1 2 3 4 5 6 7 ROW END ADDR MSB LSB ROW START ADDR MSB LSB COLN 3 ROW 10 Row 10 Coln 4 WEN CCS1 COL START ADDR MSB LSB COLN 4 0 1 2 3 4 5 6 7 ROW 10 VPOL Bit 2 WEN — This bit enables the background Window 2 generation when it is set. Bit 1 CCS1 — This additional color select bit provides the characters residing within Window 2 with two extra color selections, making a total of four selections for that row. Bit 0 VPOL — This bit selects the polarity of the incoming vertical sync signal (VFLB) on Pin 5. If it is negative polarity, clear this bit. Otherwise, set this bit to 1 to represent the posi- tive V sync signal. After power–on, this bit is cleared. Row 10 Coln 5 RG COL END ADDR MSB LSB COLN 5 0 1 2 3 4 5 6 7 B ROW 10 Bit 2–0 R, G and B — These bits control the color of Win- dow 2. Window 1 occupies Columns 0–2 of Row 10; Window 2 occupies Columns 3–5; and Window 3 occupies Columns 6–8. Window 1 has the highest priority, and Window 3 the least. If window overlapping occurs, the higher priority win- dow will cover the lower one, and the higher priority color will take over on the overlap window area. If the start address is greater than the end address, this window will not be dis- played. Window 3 Registers Row 10 Coln 6 0 1 2 3 4 5 6 7 ROW END ADDR MSB LSB ROW START ADDR MSB LSB COLN 6 ROW 10 |
同様の部品番号 - MC141541 |
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同様の説明 - MC141541 |
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