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TMP105YZCTG4 データシート(PDF) 8 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
部品番号 TMP105YZCTG4
部品情報  Digital Temperature Sensor with Two-Wire Interface
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メーカー  BURR-BROWN [Burr-Brown (TI)]
ホームページ  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

TMP105YZCTG4 データシート(HTML) 8 Page - Burr-Brown (TI)

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TMP105
SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006
www.ti.com
8
SERIAL BUS ADDRESS
To communicate with the TMP105, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation.
The TMP105 features one address pin allowing up to two
devices to be connected per bus. Pin logic levels are
described in Table 11. The address pin of the TMP105 is
read after reset, at start of communication, or in response
to a Two-Wire address acquire request. Following reading
of the state of the pin, the address is latched to minimize
power dissipation associated with detection.
A0
SLAVE ADDRESS
0
1001000
1
1001001
Table 11. Address Pin and Slave Addresses for
the TMP105
BUS OVERVIEW
The device that initiates the transfer is called a master, and
the devices controlled by the master are slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as
any change in SDA while SCL is HIGH will be interpreted
as a control signal.
Once all data has been transferred, the master generates
a STOP condition, indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
WRITING/READING TO THE TMP105
Accessing a particular register on the TMP105 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W bit LOW. Every write operation to the TMP105
requires a value for the Pointer Register. (Refer to
Figure 5.)
When reading from the TMP105, the last value stored in
the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new
value must be written to the Pointer Register. This is
accomplished by issuing a slave address byte with the
R/W bit LOW, followed by the Pointer Register byte. No
additional data are required. The master can then
generate a START condition and send the slave address
byte with the R/W bit HIGH to initiate the read command.
See Figure 6 for details of this sequence. If repeated reads
from the same register are desired, it is not necessary to
continually send the Pointer Register byte, as the TMP105
remembers the Pointer Register value until it is changed
by the next write operation.
Note that register bytes are sent most significant byte first,
followed by the least significant byte.


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