データシートサーチシステム |
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MC10110L データシート(PDF) 1 Page - Motorola, Inc |
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MC10110L データシート(HTML) 1 Page - Motorola, Inc |
1 / 4 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–40 REV 6 © Motorola, Inc. 1996 9/96 Dual 3-Input/3-Ouput OR Gate The MC10110 is designed to drive up to three transmission lines simul– taneously. The multiple outputs of this device also allow the wire “OR”–ing of several levels of gating for minimization of gate and package count. The ability to control three parallel lines from a single point makes the MC10110 particularly useful in clock distribution applications where minimum clock skew is desired. Three VCC pins are provided and each one should be used. PD = 80 mW typ/pkg (No Load) tpd = 2.4 ns typ (All Outputs Loaded) tr, tf = 2.2 ns typ (20%–80%) LOGIC DIAGRAM VCC1 = PIN 1, 15 VCC2 = PIN 16 VEE = PIN 8 12 11 10 9 13 14 2 7 6 5 3 4 MC10110 DIP PIN ASSIGNMENT VCC1 AOUT AOUT AOUT AIN AIN AIN VEE VCC2 VCC1 BOUT BOUT BOUT BIN BIN BIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–36 of the Motorola MECL Data Book (DL122/D). L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 |
同様の部品番号 - MC10110L |
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同様の説明 - MC10110L |
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