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MC14042BD データシート(PDF) 3 Page - Motorola, Inc |
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MC14042BD データシート(HTML) 3 Page - Motorola, Inc |
3 / 6 page MOTOROLA CMOS LOGIC DATA MC14042B 158 SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Min Typ # Max Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL 5.0 10 15 — — — 100 50 40 200 100 80 ns Propagation Delay Time, D to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns tPLH, tPHL 5.0 10 15 — — — 220 90 60 440 180 120 no Propagation Delay Time, Clock to Q, Q tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns tPLH, tPHL 5.0 10 15 — — — 220 90 60 440 180 120 ns Clock Pulse Width tWH 5.0 10 15 300 100 80 150 50 40 — — — ns Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 10 15 — — — — — — 15 5.0 4.0 µs Hold Time th 5.0 10 15 100 50 40 50 25 20 — — — ns Setup Time tsu 5.0 10 15 50 30 25 0 0 0 — — — ns * The formulas given are for the typical characteristics only at 25 _C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram (Data to Output) VDD VSS PULSE GENERATOR 1 16 5 6 4 7 13 14 CLOCK POLARITY D0 D1 D2 D3 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 15 1 12 11 9 10 3 2 8 For Power Dissipation test, each output is loaded with capacitance CL. 1 f 20 ns 20 ns DATA INPUT Q OUTPUT Q OUTPUT tPLH tPHL tTLH tTHL tTLH tTHL 90% 50% 10% 50% 90% 10% 90% 10% 50% tPHL |
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同様の説明 - MC14042BD |
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