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TPA5051RSARG4 データシート(PDF) 5 Page - Texas Instruments |
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TPA5051RSARG4 データシート(HTML) 5 Page - Texas Instruments |
5 / 21 page www.ti.com Serial Audio Input Ports th1 tsu1 tsu2 th2 DATA BCLK (Input) LRCLK (Input) APPLICATION INFORMATION AUDIO SERIAL INTERFACE AUDIO DATA FORMATS AND TIMING TPA5051 SLOS497A – JUNE 2006 – REVISED JULY 2006 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCLKIN Frequency, BCLK 32 × fs, 48 × fs, 64 × fs 1.024 12.288 MHz tsu1 Setup time, LRCLK to BCLK rising edge 10 ns th1 Hold time, LRCLK from BCLK rising edge 10 ns tsu2 Setup time, DATA to BCLK rising edge 10 ns th2 Hold time, DATA from BCLK rising edge 10 ns LRCLK frequency 32 48 192 kHz BCLK duty cycle 50% LRCLK duty cycle 50% BCLK rising edges between LRCLK rising edges LRCLK duty cycle = 50% 32 64 BCLK edges Figure 3. Serial Data Interface Timing The audio serial interface for the TPA5051 consists of two 3-wire synchronous serial ports. Each includes an LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on the DATA line into the serial shift register of the audio interface. Serial data is clocked into the TPA5051 on the rising edge of BCLK. LRCLK is the serial audio left/right word clock, operated at the sampling frequency, fs. It is used to latch serial data into the internal registers of the serial audio interface. BCLK can be operated at 32 to 64 times the sampling frequency for right-justified, left-justified, and I2S formats. Generally, both LRCLK and BCLK should be synchronous to the system clock. However, the TPA5051 does not have a system clock, so the only synchonization necessary is between BCLK and LRCLK. The TPA5051 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The data formats are shown in Figure 4. Data formats are selected using the I2C interface and register map (see Table 1). 5 Submit Documentation Feedback |
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