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SN74AC573DBRE4 データシート(PDF) 1 Page - Texas Instruments |
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SN74AC573DBRE4 データシート(HTML) 1 Page - Texas Instruments |
1 / 13 page SN54AC573, SN74AC573 OCTAL DTYPE TRANSPARENT LATCHES WITH 3STATE OUTPUTS SCAS542D - OCTOBER 1995 − REVISED OCTOBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 9 ns at 5 V D 3-State Outputs Drive Bus Lines Directly description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D Inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74AC573N SN74AC573N SOIC − DW Tube SN74AC573DW AC573 SOIC − DW Tape and reel SN74AC573DWR AC573 −40 °C to 85°C SOP − NS Tape and reel SN74AC573NSR AC573 −40 C to 85 C SSOP − DB Tape and reel SN74AC573DBR AC573 TSSOP − PW Tube SN74AC573PW AC573 TSSOP − PW Tape and reel SN74AC573PWR AC573 CDIP − J Tube SNJ54AC573J SNJ54AC573J −55 °C to 125°C CFP − W Tube SNJ54AC573W SNJ54AC573W −55 C to 125 C LCCC − FK Tube SNJ54AC573FK SNJ54AC573FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54AC573 ...J OR W PACKAGE SN74AC573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2Q 3Q 4Q 5Q 6Q 3D 4D 5D 6D 7D SN54AC573 . . . FK PACKAGE (TOP VIEW) |
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