MC10E197

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10

Calculations For a 2:7 Coding Scheme

Introduction

The circuit component values are calculated for a 2:7

coding scheme employing a data rate of 23 Mbit/sec. Since

the number of bits is doubled when the data is encoded, the

data clock is at half the frequency of the RDCLK signal.

Thus, the operating frequency for these calculations is

46 MHz. Further, the pole and zero positions are a function

of the data rate; hence, the component values derived by

these calculations must be scaled if a different operating

frequency is used. Finally, it should be noted that the values

are optimized for settling time.

The analysis is divided into three parts: static pole

positioning, dynamic pole positioning, and dynamic zero

positioning. Dynamic poles and zeros are those which the

designer may position, to yield the desired dynamic

response, through the judicious choice of element values.

Static poles are not directly controlled by the choice of

component values.

Static Poles

Each op-amp introduces a pair of “static” complex

conjugate poles which must lie beyond the crossover

frequency. As obtained from the data sheets and laboratory

measurements, the two open loop poles for the MC34182D

are:

Performing a root locus analysis and following the two

guidelines previously stated, an acceptable pole set is:

Both op-amps introduce a set of static complex conjugate

poles at these positions for a total of four poles. Further, the

loop gain for each op-amp associated with these pole

positions is determined from the root locus analysis to be:

V

V

In addition to the op-amps, the integrator and the VCO each

contribute a static pole at the origin. Thus, there are a total

of six static poles.

Dynamic Poles

The filter input and the voltage divider sections each

contribute a dynamic pole. As stated previously, the filter

input pole should be positioned midway between the unity

crossover point and the phase detector sampling frequency.

Hence, the open loop filter input pole position is selected as:

The voltage divider pole is set approximately one octave

higher than the filter input pole. Thus the open loop voltage

divider pole position is picked to be:

Dynamic Zero

Finally, the zero is positioned much less than one decade

before the crossover frequency; for this design the zero is

placed at:

z = − 311Hz

Once the dynamic pole and zero positions have been

determined, the phase margin is determined using a Bode

plot; if the phase margin is not sufficient, the dynamic poles

may be moved to improve the phase margin. Finally, a root

locus analysis is performed to obtain the optimum closed

loop pole positions for the dynamic characteristics of

interest.

Component Values

Having determined the closed loop pole and zero

positions the component values are calculated. From the root

locus analysis the dynamic pole and zero positions are:

z = − 311Hz

Filter Input Subsection

Rearranging Equation 4:

1

and substituting 573 kHz for the pole position and 1 kΩ for

the resistor value yields:

Augmenting Integrator Subsection

Rearranging Equation 6:

1

and substituting 311 Hz for the zero position and 0.1 μF for

the capacitor value yields:

From Equation 7 the value for the other resistors associated