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MC100EP445FAR2G データシート(PDF) 2 Page - ON Semiconductor |
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MC100EP445FAR2G データシート(HTML) 2 Page - ON Semiconductor |
2 / 18 page MC10EP445, MC100EP445 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1234 5678 24 23 22 21 20 19 18 17 16 Figure 1. 32−Lead LQFP Pinout (Top View) Warning: All VCC and VEE pins must be externally con- nected to Power Supply to guarantee proper operation. Table 1. PIN DESCRIPTION Pin SINA*, SINA* Function ECL Differential Serial Data Input A SINSEL* Q0−Q7 ECL Parallel Data Outputs ECL Serial Input Selector Pin CLK*, CLK* ECL Differential Clock Inputs PCLK, PCLK ECL Differential Parallel Clock Output SYNC* ECL Conversion Synchronizing Input CKSEL* ECL Clock Input Selector Pin VBB0, VBB1 Output Reference Voltage VCC Positive Supply VEE Negative Supply SINSEL VCC VEE SINA SINB VEE Q3 Q4 Q5 Q6 Q7 MC10EP445 MC100EP445 VCC SINB VBB0 SINA VCC SINB*, SINB* ECL Differential Serial Data Input B CKEN* ECL Clock Enable Pin RESET* ECL Reset Pin * Pins will default logic LOW or differential logic LOW when left open. Table 2. TRUTH TABLE PIN FUNCTION High Low SINSEL Select SINB Input Select SINA Input CKSEL Q: PCLK = 8:1 CLK: Q = 1:1 Q CLK Q: PCLK = 8:1 CLK: Q = 1:2 Q CLK CKEN Synchronously Disable Internal Clock Circuitry Synchronously Enable Internal Clock Circuitry RESET Asynchronous Master Reset Synchronous Enable SYNC Asynchronously Applied to Swallow a Data Bit Normal Conversion Process |
同様の部品番号 - MC100EP445FAR2G |
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同様の説明 - MC100EP445FAR2G |
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