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MC100LVEP11DR2 データシート(PDF) 2 Page - ON Semiconductor |
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MC100LVEP11DR2 データシート(HTML) 2 Page - ON Semiconductor |
2 / 12 page MC10LVEP11, MC100LVEP11 http://onsemi.com 2 1 2 3 45 6 7 8 D VEE VCC Q0 D Q1 Q1 Q0 Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION PIN FUNCTION D*, D** ECL Data Inputs Q0, Q0, Q1, Q1 ECL Data Outputs VCC Positive Supply VEE Negative Supply EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. *Pins will default to 2/3 VCC when left open. **Pins will default LOW when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 110 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
同様の部品番号 - MC100LVEP11DR2 |
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同様の説明 - MC100LVEP11DR2 |
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