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CD4021BCN データシート(PDF) 4 Page - Fairchild Semiconductor

部品番号 CD4021BCN
部品情報  8-Stage Static Shift Register
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
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AC Electrical Characteristics (Note 6)
TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ
Note 6: AC Parameters are guaranteed by DC correlated testing.
Note 7: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPLH, tPHL
Propagation Delay Time
VDD = 5V
240
350
ns
VDD = 10V
100
175
VDD = 15V
70
140
tTHL, tTLH
Transition Time
VDD = 5V
100
200
ns
VDD = 10V
50
100
VDD = 15V
40
80
fCL
Maximum Clock
VDD = 5V
2.5
3.5
MHz
Input Frequency
VDD = 10V
5
10
VDD = 15V
8
16
tW
Minimum Clock
VDD = 5V
100
200
ns
Pulse Width
VDD = 10V
50
100
VDD = 15V
40
80
trCL, tfCL
Clock Rise and
VDD = 5V
15
µs
Fall Time (Note 6)
VDD = 10V
15
VDD = 15V
15
ts
Minimum Set-Up Time
Serial Input
VDD = 5V
60
120
ns
tH ≥ 200 ns
VDD = 10V
40
80
(Ref. to CL)
VDD = 15V
30
60
Parallel Inputs
VDD = 5V
25
50
ns
tH ≥ 200 ns
VDD = 10V
15
30
(Ref. to P/S)
VDD = 15V
10
20
tH
Minimum Hold Time
VDD = 5V
0
ns
Serial In, Parallel In, ts ≥ 400 ns VDD = 10V
10
Parallel/Serial Control
VDD = 15V
15
tWH
Minimum P/S
VDD = 5V
150
250
ns
Pulse Width
VDD = 10V
75
125
VDD = 15V
50
100
tREM
Minimum P/S Removal
VDD = 5V
100
200
ns
Time (Ref. to CL)
VDD = 10V
50
100
VDD = 15V
40
80
CI
Average Input Capacitance
Any Input
5
7.5
pF
CPD
Power Dissipation
100
pF
Capacitance (Note 8)


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