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MC100EPT25DTR2G データシート(PDF) 1 Page - ON Semiconductor |
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MC100EPT25DTR2G データシート(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 14 1 Publication Order Number: MC100EPT25/D MC100EPT25 −3.3V / −5VDifferential ECL to +3.3V LVTTL Translator Description The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small outline 8−lead package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT25 to also be used in a single−ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non−inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 mF capacitor. Features • 1.1 ns Typical Propagation Delay • Maximum Frequency > 275 MHz Typical • Operating Range: VCC = 3.0 V to 3.6 V; VEE = −5.5 V to −3.0 V; GND = 0 V • 24 mA TTL Outputs • Q Output Will Default LOW with Inputs Open or at VEE • VBB Output • Open Input Default State • Safety Clamp on Inputs • Pb−Free Packages are Available A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP−8 DT SUFFIX CASE 948R ALYWG G KP25 1 8 1 8 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION 1 8 KPT25 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 (Note: Microdot may be in either location) |
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同様の説明 - MC100EPT25DTR2G |
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