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MC10123FN データシート(PDF) 1 Page - ON Semiconductor |
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MC10123FN データシート(HTML) 1 Page - ON Semiconductor |
1 / 4 page © Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10123/D MC10123 Triple 4-3-3-Input Bus Driver The MC10123 consists of three NOR gates designed for bus driving applications on card or between cards. Output low logic levels are specified with VOL = –2.1 Vdc so that the bus may be terminated to –2.0 Vdc. The gate output, when low, appears as a high impedance to the bus, because the output emitter– followers of the MC10123 are “turned–off.” This eliminates discontinuities in the characteristic impedance of the bus. The VOH level is specified when driving a 25–ohm load terminated to –2.0 Vdc, the equivalent of a 50–ohm bus terminated at both ends. Although 25 ohms is the lowest characteristic impedance that can be driven by the MC10123, higher impedance values may be used with this part. A typical 50–ohm bus is shown in Figure 1. • P D = 310 mW typ/pkg (No Load) • t pd = 3.0 ns typ • t r, tf = 2.5 ns typ (20%–80%) LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 14 12 13 15 11 9 10 2 7 5 3 6 4 FIGURE 1 — 50–OHM BUS DRIVER (TYPICAL APPLICATION) 1/3 MC10123 1/3 MC10123 1/3 MC10123 ZO = 50 Ω –2.0 VDC RECEIVERS (MECL GATES) –2.0 VDC 50 Ω 50 Ω DIP PIN ASSIGNMENT VCC1 BOUT AOUT AIN AIN AIN AIN VEE VCC2 COUT CIN CIN CIN BIN BIN BIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10123L CDIP–16 25 Units / Rail MC10123P PDIP–16 25 Units / Rail MC10123FN PLCC–20 46 Units / Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620 MC10123L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10123 AWLYYWW 1 1 16 MC10123P AWLYYWW |
同様の部品番号 - MC10123FN |
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同様の説明 - MC10123FN |
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