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MC3479PG データシート(PDF) 6 Page - ON Semiconductor |
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MC3479PG データシート(HTML) 6 Page - ON Semiconductor |
6 / 10 page MC3479 http://onsemi.com 6 VD This pin allows for provision of a current path for the motor coil current during switching, in order to suppress back−EMF voltage spikes. VD is normally connected to VM (Pin 16) through a diode (zener or regular), a resistor, or directly. The peaks instantaneous voltage at the outputs must not exceed VM by more than 6.0 V. The voltage drop across the internal clamping diodes must be included in this portion of the design (see Figure 6). Note the parasitic diodes (Figure 5) across each QL of each output provide for a complete circuit path for the switched current. Figure 6. Clamp Diode Characteristics ID (mA) 300 100 200 0 0 1.0 2.0 3.0 Full/Half Step When this input is at a Logic “0” (< 0.8 V), the outputs change a full step with each clock cycle, with the sequence direction depending on the CW/CCW input. There are four steps (Phase A, B, C, D) for each complete cycle of the sequencing logic. Current flows through both motor coils during each step, as shown in Figure 7. When taken to a Logic “1” (>2.0 V), the outputs change a half step with each clock cycle, with the sequence direction depending on the CW/CCW input. Eight steps (Phase A to H) result for each complete cycle of the sequencing logic. Phase A, C, E and G correspond (in polarity) to Phase A, B, C, and D, respectively, of the full step sequence. Phase B, D, F and H provide current to one motor coil, while de−energizing the other coil. The condition of the outputs of the de−energized coil depends on the OIC input, see Figure 7 timing diagram. OIC The output impedance control input determines the output impedance to the de−energized coil when operating in the half−step mode. When the outputs are in Phase B, D, F or H (Figure 7) and this input is at a Logic “0” (<0.8 V), the two outputs to the de−energized coil are in a high impedance condition − QL and QH of both outputs (Figure 5) are off. When this input is at a Logic “1” (>2.0 V), a low impedance output is provided to the de−energized coil as both outputs have QH on (QL off). To complete the low impedance path requires connecting VD to VM as described elsewhere in this data sheet. Bias/Set This pin can be used for three functions: a) determining the maximum output sink current; b) setting the internal logic to a known state; and c) reducing power consumption. a) The maximum output sink current is determined by the base drive current supplied to the lower transistors (QLs of Figure 5) of each output, which in turn, is a function of IBS. The appropriate value of IBS can be approximated using Figure 11. |
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同様の説明 - MC3479PG |
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