データシートサーチシステム |
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MC10173 データシート(PDF) 1 Page - ON Semiconductor |
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MC10173 データシート(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10173/D MC10173 Quad 2-Input Multiplexer/ Latch The MC10173 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables data inputs D01, D11, D21, D31. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. • P D = 275 mW typ/pkg (No Load) • t pd = 2.5 ns typ • t r, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM VCC = PIN 16 VEE = PIN 8 1 Q0 2 Q1 15 Q2 14 Q3 SELECT 9 D00 6 D01 5 D10 4 D11 3 D20 13 D21 12 D30 11 D31 10 CLOCK 7 TRUTH TABLE SELECT CLOCK Q0n+1 H L D00 L L D01 X H Q0n http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10173L CDIP–16 25 Units / Rail MC10173P PDIP–16 25 Units / Rail MC10173FN PLCC–20 46 Units / Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620 MC10173L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10173 AWLYYWW 1 1 16 MC10173P AWLYYWW DIP PIN ASSIGNMENT Q0 Q1 D11 D10 D01 D00 CLOCK VEE VCC Q2 Q3 D20 D21 D30 D31 SELECT 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). |
同様の部品番号 - MC10173_02 |
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同様の説明 - MC10173_02 |
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