データシートサーチシステム |
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ATMEGA162V データシート(PDF) 52 Page - ATMEL Corporation |
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ATMEGA162V データシート(HTML) 52 Page - ATMEL Corporation |
52 / 325 page 52 ATmega162/V 2513I–AVR–02/07 Figure 25. Brown-out Reset During Operation Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 53 for details on operation of the Watchdog Timer. Figure 26. Watchdog Reset During Operation MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. VCC RESET TIME-OUT INTERNAL RESET VBOT- VBOT+ tTOUT CK CC Bit 765 432 10 JTD – SM2 JTRF WDRF BORF EXTRF PORF MCUCSR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description |
同様の部品番号 - ATMEGA162V_07 |
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同様の説明 - ATMEGA162V_07 |
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