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ATTINY2313-20MU データシート(Datasheet) 30 Page - ATMEL Corporation

部品番号. ATTINY2313-20MU
部品情報  8-bit Microcontroller with 2K Bytes In-System Programmable Flash
ダウンロード  231 Pages
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メーカー  ATMEL [ATMEL Corporation]
ホームページ  http://www.atmel.com
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 30 page
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30
ATtiny2313/V
2543I–AVR–04/06
128 kHz Internal
Oscillator
The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz.
The frequency is nominal at 3 V and 25
°C. This clock may be selected as the system
clock by programming the CKSEL Fuses to 0110.
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 11.
System Clock Prescalar
The ATtiny2313 has a system clock prescaler, and the system clock can be divided by
setting the “CLKPR – Clock Prescale Register” on page 30. This feature can be used to
decrease the system clock frequency and the power consumption when the requirement
for processing power is low. This can be used with all clock source options, and it will
affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O, clkCPU,
and clk
FLASH are divided by a factor as shown in Table 12 on page 32.
When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occurs in the clock system. It also ensures that no intermediate frequency is
higher than neither the clock frequency corresponding to the previous setting, nor the
clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes
to switch from one clock division to the other cannot be exactly predicted. From the time
the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, two active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler
setting.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write pro-
cedure is not interrupted.
CLKPR – Clock Prescale
Register
Table 11. Start-up Times for the 128 kHz Internal Oscillator
SUT1..0
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset
Recommended Usage
00
6 CK
14CK
BOD enabled
01
6 CK
14CK + 4 ms
Fast rising power
10
6 CK
14CK + 64 ms
Slowly rising power
11
Reserved
Bit
7
6
5
4
3
210
(0x61)
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
See Bit Description




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