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FIN1217MTD データシート(PDF) 5 Page - Fairchild Semiconductor

部品番号 FIN1217MTD
部品情報  LVDS 21-Bit Serializers/De-Serializers
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN1217MTD データシート(HTML) 5 Page - Fairchild Semiconductor

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Truth Tables
Transmitter Truth Table
H
HIGH Logic Level
L
LOW Logic Level
X
Don’t Care
Z
High Impedance
F
Floating
Note 2: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V.
Note 3: TxCLKOut
r will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z).
Receiver Truth Table
H
HIGH Logic Level
L
LOW Logic Level
P
Last Valid State
X
Don’t Care
Z
High Impedance
F
Failsafe Condition
Note 4: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V.
Note 5: Failsafe condition is defined as the input being terminated and un-driven (Z) or shorted or open.
Note 6: If RxCLKIn
r is removed prior to the RxInr data being removed, RxOut will be the last valid state. If RxInr data is removed prior to RxCLKInr being
removed, RxOut will be HIGH.
Inputs
Outputs
TxIn
TxCLKIn
PwrDn (Note 2)
TxOut
r
TxCLKOut
r
Active
Active
H
L/H
L/H
Active
L/H/Z
H
L/H
X (Note 3)
FActive
H
L
L/H
F
F
H
L
X (Note 3)
XX
L
Z
Z
Inputs
Outputs
RxIn
r
RxCLKIn
r
PwrDn (Note 4)
RxOut
RxCLKOut
Active
Active
H
L/H
L/H
Active
F (Note 5)
H
P
H
F (Note 5)
Active
H
H
L/H
F (Note 5)
F (Note 5)
H
P (Note 6)
H
XX
L
L
H


同様の部品番号 - FIN1217MTD

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