データシートサーチシステム |
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74F112SJ データシート(PDF) 2 Page - Fairchild Semiconductor |
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74F112SJ データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Unit Loading/Fan Out Truth Table H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q0(Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL J1, J2, K1, K2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP1, CP2 Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA Q1, Q2, Q1, Q2 Outputs 50/33.3 −1 mA/20 mA Inputs Outputs SD CD CP JK Q Q LH X X X H L HL X X X L H LL X X X H H HH hh Q0 Q0 HH lh L H HH hl H L HH ll Q0 Q0 |
同様の部品番号 - 74F112SJ |
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同様の説明 - 74F112SJ |
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