データシートサーチシステム |
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74VCXR162601MTD データシート(PDF) 2 Page - Fairchild Semiconductor |
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74VCXR162601MTD データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Function Table (Note 2) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = HIGH Impedance Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 3: Output level before the indicated steady-state input conditions were established Note 4: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Logic Diagram Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A1–A18 Side A Inputs or 3-STATE Outputs B1–B18 Side B Inputs or 3-STATE Outputs Inputs Outputs CLKENAB OEAB LEAB CLKAB An Bn XH X X X Z XL H X L L XL H X H H HL L X X B0 (Note 3) HL L X X B0 (Note 3) LL L ↑ LL LL L ↑ HH LL L L X B0 (Note 3) LL L H X B0 (Note 4) |
同様の部品番号 - 74VCXR162601MTD |
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同様の説明 - 74VCXR162601MTD |
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