6

FN8091.0

December 14, 2006

Timing Diagrams

Bus Timing

Write Cycle Timing

NOTES:

1. Equation 1 governs the output voltage and is stated as follows:

Rpu

SDA and SCL Bus Pull-up Resistor

Off-chip

For Cb = 400pF, max is about

2~2.5k

Ω

For Cb = 40pF, max is about

15~20k

Ω

1k

Ω

1µA

A1, A0, SHDN, SDA, and SCL Input

Buffer LOW Voltage

-0.3

V

A1, A0, SHDN, SDA, and SCL Input

Buffer HIGH Voltage

V

SDA Output Buffer LOW Voltage

sink

00.4

V

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

(Note 3)

10

400

pF

EEPROM Endurance

1,000,000

Cycles

EEPROM Retention

Temperature T

≤ +55°C

50

Years

(Note 14)

Non-Volatile Write Cycle Time

12

20

ms

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

(Note 2)

MAX

UNITS

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

SCL

SDA

8th BIT OF LAST BYTE

ACK

STOP

CONDITION

START

CONDITION

V

OUT

A

V

V

REF

n

255

----------

•

KT

T

0

–

() 2m

•

() 255

–

255

--------------------------------

+

⎩⎭

⎨⎬

⎧⎫

•

n = 0 to 255, m = 0 to 255, K = -2.1mV/C(typ), T0 = +25

°C

,

=

ISL21400