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AD5522JSVUZ データシート(PDF) 23 Page - Analog Devices |
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AD5522JSVUZ データシート(HTML) 23 Page - Analog Devices |
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23 / 48 page  Preliminary Technical Data AD5522 Rev. PrM | Page 23 of 48 DAC LEVELS Each channel contains five dedicated DAC levels : one for the force amplifier, one each for the clamp high and low levels and one each for the comparator high and low levels. The architecture of a single DAC channel consists of a 16-bit resistor-string DAC followed by an output buffer amplifier. This resistor-string architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The transfer function for DAC outputs is: DUTGND CODE OFFSETDAC V DACCODE V V REF REF OUT + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ − ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = 16 16 2 5 . 3 2 5 . 4 Where the voltage range must be take into account the +/-4V headroom and footroom requirements for the amplifier and sense resistor and must be within the range -16.25V to 22.5V (22V range + 500mV overrange to allow for correction). OFFSET DAC The device is capable of forcing a 22.5V (4.5 × VREF) voltage range. Included on chip is one 16 Bit offset DAC (one for all four channels) which allows for adjustment of the voltage range. The useable range is -16.25V to 22.5V. Zero scale gives a full- scale range of 0V to +22.5V, mid scale gives ±11.25V, while the most negative useful range is in a range of -16.25V to 6.25V. Full scale loaded to the Offset DAC does not give a useful output voltage range as the output amplifiers are limited by available footroom. The following table shows the effect of the Offset DAC on the other DACs in the device. Table 11. OFFSET DAC Relationship with other DACs with VREF = 5V Offset DAC Code DAC Code DAC Output Voltage Range 0 0 0.00 V 0 32768 11.25 V 0 65535 22.50 V 32768 0 -8.75 V 32768 32768 2.50 V 32768 65535 13.75 V 42130 0 -11.25 V 42130 32768 0.00 V 42130 65535 11.25 V 60855 0 -16.25 60855 32768 -5.00 60855 65535 6.25 65535 - Footroom Limitations Therefore, depending on headroom available, the input to the Force Amplifier may be unipolar positive, or bipolar, either symmetrical or asymmetrical about DUTGND but always within a voltage span of 22.5V. The offset DAC offsets all DAC functions. It also centers the current range, such that zero current always flows at midscale code irrespective of offset DAC setting. Rearranging the transfer function for the DAC output gives the following equation to determine what Offset DAC code is required for a given reference and output voltage range. ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ × − ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − = ⋅ 5 . 3 5 . 4 5 . 3 ) ( 2 16 DACCODE V DUTGND V CODE OFFSETDAC REF OUT OFFSET AND GAIN REGISTERS Each DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain, including the DAC, using the internal m and c registers, which hold the correction factors. All registers in the AD5522 are volatile, so need to be loaded on power on during a calibration cycle. The digital input transfer function for each DAC can be represented as x2 = [(m + 1)/ 2n × x1] + (c – 2n – 1) where: x2 = the data-word loaded to the resistor string DAC. x1 = the 16-bit data-word written to the DAC input register. m = code in gain register (default code = 216 – 1.) c = code in offset register (default code = 215) n = DAC resolution (n = 16). The calibration engine is only engaged when data is written to the x1 register. This has the advantage of minimizing the setup time of the device. CACHED X2 REGISTERS Each DAC has a number of cached x2 values. These registers store the result of an offset and gain calibration in advance of a mode change. This enables the user to preload registers; allow the calibration engine to calculate the appropriate x2 value and store until ready to change modes. As the data is ready and held in the appropriate register, this enables mode changing be as time efficient as possible. If an update occurs to a DAC register set that is currently part of the operating PMU mode, the DAC output will update immediately (depending on LOAD condition). |
同様の部品番号 - AD5522JSVUZ |
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同様の説明 - AD5522JSVUZ |
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