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AD9910BSVZ-REEL データシート(PDF) 7 Page - Analog Devices

部品番号 AD9910BSVZ-REEL
部品情報  1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9910BSVZ-REEL データシート(HTML) 7 Page - Analog Devices

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AD9910
Rev. 0 | Page 7 of 60
Parameter
Conditions/Comments
Min
Typ
Max
Unit
CMOS LOGIC INPUTS
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
90
120
μA
Logic 0 Current
38
50
μA
Input Capacitance
2
pF
CMOS LOGIC OUTPUTS
1 mA load
Logic 1 Voltage
2.8
V
Logic 0 Voltage
0.4
V
POWER SUPPLY CURRENT
IAVDD (1.8 V)
110
mA
IAVDD (3.3 V)
29
mA
IDVDD (1.8 V)
222
mA
IDVDD (3.3 V)
11
mA
TOTAL POWER CONSUMPTION
Single Tone Mode
715
850
mW
Rapid Power-Down Mode
330
400
mW
Full Sleep Mode
19
25
mW
1 The gain value for VCO range Setting 5 is measured at 1000 MHz.
2 Wake-up time refers to the recovery from analog power-down. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference. The wake-
up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.


同様の部品番号 - AD9910BSVZ-REEL

メーカー部品番号データシート部品情報
logo
Analog Devices
AD9910BSVZ-REEL AD-AD9910BSVZ-REEL Datasheet
1Mb / 64P
   CMOS Direct Digital Synthesizer
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