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SM65MLVD205AD データシート(PDF) 9 Page - Texas Instruments |
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SM65MLVD205AD データシート(HTML) 9 Page - Texas Instruments |
9 / 26 page www.ti.com A/Y B/Z 0 V or VCC 1.62 k Ω , ±1% VA, VB, VY or VZ tc(n) 1/f0 0 V 0 V Period Jitter 0 V Diff Peak to Peak Jitter 1/f0 PRBS INPUT OUTPUT VA -VB or VY -VZ VA -VB or VY -VZ CLOCK INPUT IDEAL OUTPUT ACTUAL OUTPUT VCC VCC/2 tjit(per) = tc(n) -1/f0 tjit(pp) 0 V VCC VCC/2 0 V VA -VB or VY -VZ VA -VB or VY -VZ (VA + VB)/2 IO R VCM VO VID VA IA A B IB VB SN65MLVD200A, SN65MLVD202A SN65MLVD204A, SN65MLVD205A SLLS573 – DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION (continued) Figure 7. Maximum Steady State Output Voltage A. All input pulses are supplied by an Agilent 81250 Stimulus System. B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software C. Period jitter is measured using a 50 MHz 50 ±1% duty cycle clock input. D. Peak-to-peak jitter is measured using a 100Mbps 215–1 PRBS input. Figure 8. Driver Jitter Measurement Waveforms Figure 9. Receiver Voltage and Current Definitions 9 Submit Documentation Feedback |
同様の部品番号 - SM65MLVD205AD |
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同様の説明 - SM65MLVD205AD |
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