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TDA10045 データシート(PDF) 7 Page - NXP Semiconductors |
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TDA10045 データシート(HTML) 7 Page - NXP Semiconductors |
7 / 20 page 2001 Nov 08 7 Philips Semiconductors Product specification DVB-T channel receiver TDA10045H DEN 65 O output data validation signal; active HIGH during the valid and regular data bytes OCLK 66 O output clock; OCLK is the output clock for the parallel DO[7:0] outputs DO[7:5] 67 to 69 O output data carrying the current sample of the current MPEG2 packet (188 bytes), delivered on the rising edge of OCLK by default when the serial mode is selected. The output data is delivered by DO[0]. VDDD18 70 − digital supply voltage for the core (1.8 V typ.) VSSD 71 − digital ground supply (0 V) DO[4:0] 72 to 76 O output data carrying the current sample of the current MPEG2 packet (188 bytes), delivered on the rising edge of OCLK by default when the serial mode is selected. The output data is delivered by DO[0]. VDDD33 77 − digital supply voltage for the pads (3.3 V typ.) VSSD 78 − digital ground supply (0 V) XIN 79 I(2) crystal oscillator input pin XOUT 80 O crystal oscillator output pin; typically a fundamental crystal oscillator is connected between pins XIN and XOUT VDDD18 81 − digital supply voltage for the core (1.8 V typ.) VSSD 82 − digital ground supply (0 V) n.c. 83 − not connected VCCD(PLL) 84 − power supply input for the digital circuits of the PLL module (1.8 V typ.) DGND 85 − ground return for the digital circuits of the PLL module n.c. 86 − not connected PPLGND 87 − ground return for the analog circuits of the PLL module VCCA(PLL) 88 − power supply input for the analog circuits of the PLL module (3.3 V typ.) VSSA3 89 − ground return for the analog circuits VDDA3 90 − power supply input for the analog circuits; the DC voltage should be 3.3 V VIP 91 − positive input to the ADC; this pin is DC biased to half supply through an internal resistor divider (2 × 20 kΩ resistors). In order to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between −0.5 and +0.5 V. VIM 92 − negative input to the ADC; this pin is DC biased to half supply to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between −0.5 and +0.5 V through an internal resistor divider (2 × 20 kΩ resistors) Vref(neg) 93 − negative reference voltage for the ADC Vref(pos) 94 − positive reference voltage for the ADC VDDA3 95 − power supply input for the analog circuits; the DC voltage should be 3.3 V VSSA3 96 − ground return for analog circuits VSSA2 97 − ground return for the analog clock drivers VDDA2 98 − power supply input for the analog clock drivers; the DC voltage should be 3.3 V VSSA1 99 − ground return for the digital switching circuitry VDDD1 100 − power supply input for the digital switching circuitry; sensitive to the supply noise; the DC voltage should be 1.8 V SYMBOL PIN TYPE DESCRIPTION |
同様の部品番号 - TDA10045 |
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同様の説明 - TDA10045 |
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