データシートサーチシステム |
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FM22L16 データシート(PDF) 10 Page - Ramtron International Corporation |
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FM22L16 データシート(HTML) 10 Page - Ramtron International Corporation |
10 / 15 page FM22L16 Rev. 1.0 Mar. 2007 Page 10 of 15 Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU Power-Up to First Access Time (after VDD min) 450 - µs tPD Power-Down to Last Access Time (prior to VTP) 0 µs tVR VDD Rise Time 50 - µs/V 1,2 tVF VDD Fall Time 100 - µs/V 1,2 tZZEN Sleep Mode Enter Time (/ZZ low to /CE don’t care) - 0 µs tZZEX Sleep Mode Exit Time (/ZZ high to 1 st access after wakeup) 450 - µs Notes 1 Slope measured at any point on VDD waveform. 2 Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than 100ms through the range of 0.4V to 1.0V. Data Retention (VDD = 2.7V to 3.6V) Parameter Min Units Notes Data Retention 10 Years AC Test Conditions Input Pulse Levels 0 to 3V Input rise and fall times 3 ns Input and output timing levels 1.5V Output Load Capacitance 30pF Read Cycle Timing 1 (/CE low, /OE low) Read Cycle Timing 2 (/CE-controlled) |
同様の部品番号 - FM22L16 |
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同様の説明 - FM22L16 |
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