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LM1044 データシート(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM1044
部品情報  Analog Video Switch
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM1044 データシート(HTML) 6 Page - National Semiconductor (TI)

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Application Notes (Continued)
Truth Table
Control Logic
EN
C
B
A
Channel Selected
22
19
20
21
1
0
0
0
CV1 RGB Outputs Muted
1
0
0
1
CV2 RGB Outputs Muted
1
0
1
0
CV3 RGB Outputs Muted
1
0
1
1
RGB1 with Sync1
1
1
1
1
RGB2 with Sync2
1
1
1
0
Mute
1
1
0
1
Mute
1
1
0
0
Mute
0
X
X
X
Previous selection retained
The shaded section of the truth table indicates selection
compatible with the LM1038 four channel stereo audio
switch logic to give a possible selection of CV1 a Audio1
CV2 a Audio2 CV3 a Audio3 RGB1 a Audio4 and RGB2
a
Mute or Audio4 see
Figure 3
The mute conditions in the table correspond to disabled
CVSync (output pulled low) and high impedance RGB out-
puts which may be connected in parallel with other device
outputs for further expansion of the switch system If all the
RGB inputs are being used to switch composite video sig-
nals then the RGB outputs can be connected into the CV
inputs to allow multiplexing down to 1 output from a large
number of input signals
LOGIC AND ENABLE INPUTS
If undriven the enable input will assume a high impedance
logic 1 condition and should be defined externally The Log-
ic selection inputs have internal pulldowns typically 20 kX
which will define logic low levels if unconnected giving CV1
in default of any other control input
INPUT BIAS FOR CV CHANNELS
The CV and Sync inputs are biased via internal 15 kX and
23 kX resistors respectively to the internally generated 7V
bias (VS e 12V) level at pin 14 Input coupling capacitors
need to be chosen to give an adequate low frequency re-
sponse when driving the 15 kX input impedance for exam-
ple for less than 2% tilt on a frame rate waveform 330 mF
will be required Depending on the effectiveness of any fol-
lowing clamp circuitry the input coupling capacitors may be
reduced in value These inputs may also be driven with DC
coupled signals provided the standing DC level is sufficient-
ly near to 7V to maintain the output within the output signal
range (45 to 85V for VS e 12V)
The bias at pin 14 has a DC output resistance typically of 1
kX and requires a decoupling capacitor to properly define
the gain and crosstalk To ensure an adequate low frequen-
cy response this capacitor should be 100 mF or more This
pin may also be biased from an external voltage source
provided the output remains within the output window Note
this bias will also affect the voltage at pin 13
INPUT BIAS FOR RGB CHANNELS
The 6 RGB inputs may be biased in one of three ways
1) DC restored above an internal 45V level
2) Clamped to an internal 7V bias level
3) Driven directly with DC coupled signals
With an AC coupled input signal and the clamp pulse held
low the negative going peaks will DC restore to a level
greater than 3 diode drops below the reference bias level at
pin 13 typically 45V for VS e 12V The source resistance
of the diode restoring path is 1 kX for currents below
200 mA
Simplified Schematic of RGB Stage
TLH9252 – 6
The simplified schematic of the CV stage is virtually identical
to the RGB stage except that the CV stage does not incor-
porate the clamp circuitry
Clamping to the internal 7V bias is arranged by applying a
positive going clamp pulse to pin 18 during a time when the
input signals are at a black reference level This is usually
during the back porch or during the blanking period of sig-
nals without syncs The clamp pulse width should not be
less than 3 ms During the time pin 18 is high all six inputs
R1 R2 G1 G2 B1 and B2 are connected to the RGB bias
voltage developed at pin 13 charging the input coupling
capacitors to this level These coupling capacitors are cho-
sen to optimize value versus tilt introduced during the active
line period A value of 330 mF gives less than 1% tilt for
input currents less than 20 mA The effective impedance of
the clamp path when conducting is 300X The voltage at pin
13 is a low impedance 60X buffered version of the CV bias
voltage at pin 14 and decoupling is required to remove high
frequencies and maintain channel separation The voltage
at pin 13 may be changed by driving pin 14 as described for
CV bias
6


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